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Searched refs:mtk_ddp_write_mask (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/mediatek/
H A Dmtk_mdp_rdma.c165 mtk_ddp_write_mask(cmdq_pkt, FLD_ROT_ENABLE, &priv->cmdq_reg, in mtk_mdp_rdma_start()
173 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, in mtk_mdp_rdma_stop()
196 mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_ARGB, &priv->cmdq_reg, in mtk_mdp_rdma_config()
199 mtk_ddp_write_mask(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
202 mtk_ddp_write_mask(cmdq_pkt, cfg->addr0, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
205 mtk_ddp_write_mask(cmdq_pkt, src_pitch_y, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
210 mtk_ddp_write_mask(cmdq_pkt, FLD_OUTPUT_10B, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
212 mtk_ddp_write_mask(cmdq_pkt, FLD_SIMPLE_MODE, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
223 mtk_ddp_write_mask(cmdq_pkt, offset_y, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
225 mtk_ddp_write_mask(cmdq_pkt, cfg->width, &priv->cmdq_reg, priv->regs, in mtk_mdp_rdma_config()
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H A Dmtk_disp_rdma.c193 mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
195 mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_config()
273 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
276 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB, in mtk_rdma_layer_config()
280 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
290 mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs, in mtk_rdma_layer_config()
H A Dmtk_disp_merge.c116 mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE, in mtk_merge_fifo_setting()
120 mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16, in mtk_merge_fifo_setting()
124 mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16, in mtk_merge_fifo_setting()
188 mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs, in mtk_merge_advance_config()
190 mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs, in mtk_merge_advance_config()
H A Dmtk_drm_ddp_comp.c95 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value, in mtk_ddp_write_mask() function
197 mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
199 mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
201 mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs, in mtk_dsc_config()
210 mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN); in mtk_dsc_start()
H A Dmtk_ethdr.c192 mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx), in mtk_ethdr_layer_config()
194 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON, in mtk_ethdr_layer_config()
242 mtk_ddp_write_mask(cmdq_pkt, MIX_SRC_L0_EN, &mixer->cmdq_base, mixer->regs, in mtk_ethdr_config()
H A Dmtk_disp_ovl.c241 mtk_ddp_write_mask(cmdq_pkt, enabled ? OVL_LAYER_AFBC_EN(idx) : 0, in mtk_ovl_set_afbc()
353 mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_on()
362 mtk_ddp_write_mask(cmdq_pkt, 0, &ovl->cmdq_reg, ovl->regs, in mtk_ovl_layer_off()
H A Dmtk_drm_ddp_comp.h291 void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,