| /openbmc/linux/arch/powerpc/platforms/4xx/ |
| H A D | soc.c | 35 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, addr); in l2c_diag()
62 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0); in l2c_error_handler()
126 mtdcr(dcrbase_isram + DCRN_SRAM0_DPC, in ppc4xx_l2c_probe()
128 mtdcr(dcrbase_isram + DCRN_SRAM0_SB0CR, in ppc4xx_l2c_probe()
130 mtdcr(dcrbase_isram + DCRN_SRAM0_SB1CR, in ppc4xx_l2c_probe()
132 mtdcr(dcrbase_isram + DCRN_SRAM0_SB2CR, in ppc4xx_l2c_probe()
134 mtdcr(dcrbase_isram + DCRN_SRAM0_SB3CR, in ppc4xx_l2c_probe()
141 mtdcr(dcrbase_l2c + DCRN_L2C0_CFG, r); in ppc4xx_l2c_probe()
143 mtdcr(dcrbase_l2c + DCRN_L2C0_ADDR, 0); in ppc4xx_l2c_probe()
157 mtdcr(dcrbase_l2c + DCRN_L2C0_SNP0, r); in ppc4xx_l2c_probe()
[all …]
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| H A D | uic.c | 63 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_unmask_irq()
66 mtdcr(uic->dcrbase + UIC_ER, er); in uic_unmask_irq()
80 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_irq()
106 mtdcr(uic->dcrbase + UIC_ER, er); in uic_mask_ack_irq()
116 mtdcr(uic->dcrbase + UIC_SR, sr); in uic_mask_ack_irq()
157 mtdcr(uic->dcrbase + UIC_PR, pr); in uic_set_irq_type()
158 mtdcr(uic->dcrbase + UIC_TR, tr); in uic_set_irq_type()
159 mtdcr(uic->dcrbase + UIC_SR, ~mask); in uic_set_irq_type()
263 mtdcr(uic->dcrbase + UIC_ER, 0); in uic_init_one()
264 mtdcr(uic->dcrbase + UIC_CR, 0); in uic_init_one()
[all …]
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| /openbmc/linux/arch/powerpc/boot/ |
| H A D | dcr.h | 11 #define mtdcr(rn, val) \ macro
29 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
32 mtdcr(DCRN_SDRAM0_CFGADDR, offset); \
33 mtdcr(DCRN_SDRAM0_CFGDATA, data); })
182 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
185 mtdcr(DCRN_SDR0_CONFIG_ADDR, offset); \
186 mtdcr(DCRN_SDR0_CONFIG_DATA, data); })
200 mtdcr(DCRN_CPR0_CFGADDR, offset); \
203 mtdcr(DCRN_CPR0_CFGADDR, offset); \
204 mtdcr(DCRN_CPR0_CFGDATA, data); })
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| H A D | 4xx.c | 296 mtdcr(DCRN_MAL0_CFG, MAL_RESET); in ibm4xx_quiesce_eth()
312 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i)); in ibm4xx_fixup_ebc_ranges()
609 mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1); in ibm405gp_fixup_clocks()
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| /openbmc/linux/arch/powerpc/platforms/44x/ |
| H A D | fsp2.h | 249 mtdcr(DCRN_CMU_ADDR, reg); \
250 mtdcr(DCRN_CMU_DATA, data); \
255 mtdcr(DCRN_CMU_ADDR, reg); \
261 mtdcr(DCRN_L2CDCRAI, reg); \
262 mtdcr(DCRN_L2CDCRDI, data); \
267 mtdcr(DCRN_L2CDCRAI, reg); \
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| H A D | fsp2.c | 253 mtdcr(DCRN_PLB6_BASE, val); in fsp2_probe()
254 mtdcr(DCRN_PLB6_HD, 0xffff0000); in fsp2_probe()
255 mtdcr(DCRN_PLB6_SHD, 0xffff0000); in fsp2_probe()
299 mtdcr(DCRN_CONF_EIR_RS, 0x80000000); in fsp2_probe()
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| /openbmc/linux/arch/powerpc/sysdev/ |
| H A D | dcr-low.S | 37 mtdcr 0,r4; blr
42 mtdcr dcr,r4; blr
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | dcr-native.h | 30 #define dcr_write_native(host, dcr_n, value) mtdcr(dcr_n + host.base, value)
64 #define mtdcr(rn, v) \ macro
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | cpu_setup_44x.S | 66 mtdcr DCRN_PLB4A0_ACR,r3
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 1143 #define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) macro
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| /openbmc/qemu/target/ppc/ |
| H A D | translate.c | 5927 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
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