Searched refs:mseccfg (Results 1 – 7 of 7) sorted by relevance
89 #define MSECCFG_MML_ISSET(env) get_field(env->mseccfg, MSECCFG_MML)90 #define MSECCFG_MMWP_ISSET(env) get_field(env->mseccfg, MSECCFG_MMWP)91 #define MSECCFG_RLB_ISSET(env) get_field(env->mseccfg, MSECCFG_RLB)
10 mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx6411 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
626 val |= (env->mseccfg & mask); in mseccfg_csr_write()627 if ((val ^ env->mseccfg) & mask) { in mseccfg_csr_write()640 env->mseccfg = val; in mseccfg_csr_write()648 trace_mseccfg_csr_read(env->mhartid, env->mseccfg); in mseccfg_csr_read()649 return env->mseccfg; in mseccfg_csr_read()
448 target_ulong mseccfg; member
89 return env->mseccfg & MSECCFG_MLPE; in cpu_get_fcfien()152 return get_field(env->mseccfg, MSECCFG_PMM); in riscv_pm_get_pmm()
823 if (env->mseccfg & MSECCFG_SSEED) { in seed()829 if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { in seed()831 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { in seed()
762 env->mseccfg = 0; in riscv_cpu_reset_hold()