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Searched refs:mpll_con0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c87 writel(MPLL_CON0_VAL, &clk->mpll_con0); in system_clock_init()
H A Dclock_init_exynos5.c628 writel(val, &clk->mpll_con0); in exynos5250_system_clock_init()
629 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) in exynos5250_system_clock_init()
849 writel(val, &clk->mpll_con0); in exynos5420_system_clock_init()
850 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0) in exynos5420_system_clock_init()
H A Dclock.c196 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
226 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
257 r = readl(&clk->mpll_con0); in exynos5_get_pll_clk()
315 r = readl(&clk->mpll_con0); in exynos542x_get_pll_clk()
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c213 clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); in board_clock_init()
216 while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) in board_clock_init()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclock.h188 unsigned int mpll_con0; member
391 unsigned int mpll_con0; member
574 unsigned int mpll_con0; member
1067 unsigned int mpll_con0; member
/openbmc/u-boot/board/samsung/trats/
H A Dtrats.c342 writel(MPLL_CON0_VAL, (unsigned int)&clk->mpll_con0); in board_clock_init()