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Searched refs:mmu_idx (Results 1 – 25 of 105) sorted by relevance

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/openbmc/qemu/accel/tcg/
H A Dcputlb.c147 return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; in tlb_entry()
542 int mmu_idx; in tlb_flush_page_by_mmuidx_async_0() local
549 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { in tlb_flush_page_by_mmuidx_async_0()
731 int mmu_idx; in tlb_flush_range_by_mmuidx_async_0() local
739 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { in tlb_flush_range_by_mmuidx_async_0()
936 int mmu_idx; in tlb_reset_dirty() local
939 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { in tlb_reset_dirty()
969 int mmu_idx; in tlb_set_dirty() local
975 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { in tlb_set_dirty()
979 for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { in tlb_set_dirty()
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H A Dldst_common.c.inc244 MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
249 int mmu_idx, uintptr_t ra)
262 int mmu_idx, uintptr_t ra)
289 int mmu_idx, uintptr_t ra)
309 int mmu_idx, uintptr_t ra)
311 MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
316 int mmu_idx, uintptr_t ra)
323 int mmu_idx, uintptr_t ra)
330 int mmu_idx, uintptr_t ra)
337 int mmu_idx, uintptr_t ra)
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/openbmc/qemu/target/arm/tcg/
H A Dhflags.c118 !((mmu_idx & ARM_MMU_IDX_M_NEGPRI) && in rebuild_hflags_m32()
208 ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); in rebuild_hflags_a64()
209 uint64_t tcr = regime_tcr(env, mmu_idx); in rebuild_hflags_a64()
217 tbid = aa64_va_parameter_tbi(tcr, mmu_idx); in rebuild_hflags_a64()
299 switch (mmu_idx) { in rebuild_hflags_a64()
414 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); in rebuild_hflags_internal() local
438 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); in HELPER() local
446 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); in HELPER() local
459 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); in HELPER() local
466 ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, el); in HELPER() local
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H A Dtlb_helper.c23 mmu_idx = stage_1_mmu_idx(mmu_idx); in arm_s1_regime_using_lpae_format()
24 return regime_using_lpae_format(env, mmu_idx); in arm_s1_regime_using_lpae_format()
84 ARMMMUIdx arm_mmu_idx = core_to_arm_mmu_idx(env, mmu_idx); in compute_fsr_fsc()
173 int mmu_idx, ARMMMUFaultInfo *fi) in arm_deliver_fault() argument
243 fsr = compute_fsr_fsc(env, fi, target_el, mmu_idx, &fsc); in arm_deliver_fault()
268 int mmu_idx, uintptr_t retaddr) in arm_cpu_do_unaligned_access() argument
277 arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); in arm_cpu_do_unaligned_access()
284 int mmu_idx = arm_env_mmu_index(env); in helper_exception_pc_alignment() local
318 arm_deliver_fault(cpu, addr, access_type, mmu_idx, &fi); in arm_cpu_do_transaction_failed()
322 MMUAccessType access_type, int mmu_idx, in arm_cpu_tlb_fill() argument
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H A Dmte_helper.c267 int mmu_idx = arm_env_mmu_index(env); in HELPER() local
320 int mmu_idx = arm_env_mmu_index(env); in do_stg() local
347 int mmu_idx = arm_env_mmu_index(env); in HELPER() local
357 int mmu_idx = arm_env_mmu_index(env); in do_st2g() local
405 int mmu_idx = arm_env_mmu_index(env); in HELPER() local
421 int mmu_idx = arm_env_mmu_index(env); in HELPER() local
774 int mmu_idx, ptr_tag, bit55; in mte_probe_int() local
918 int mmu_idx, bit55; in HELPER() local
1020 int mmu_idx, tag_count; in mte_mops_probe() local
1070 int mmu_idx, tag_count; in mte_mops_probe_rev() local
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H A Dm_helper.c169 ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; in arm_v7m_mmu_idx_all() local
180 mmu_idx |= ARM_MMU_IDX_M_S; in arm_v7m_mmu_idx_all()
183 return mmu_idx; in arm_v7m_mmu_idx_all()
394 ARMMMUIdx mmu_idx; in HELPER() local
665 ARMMMUIdx mmu_idx; in arm_v7m_load_vector() local
767 ARMMMUIdx mmu_idx; in v7m_push_callee_stack() local
789 mmu_idx = arm_mmu_idx(env); in v7m_push_callee_stack()
1630 ARMMMUIdx mmu_idx; in do_v7m_exception_exit() local
1925 ARMMMUIdx mmu_idx; in do_v7m_function_return() local
2092 ARMMMUIdx mmu_idx; in v7m_handle_execute_nsc() local
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/openbmc/qemu/target/mips/sysemu/
H A Dphysaddr.c25 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) in is_seg_am_mapped() argument
42 switch (mmu_idx) { in is_seg_am_mapped()
85 int mapped = is_seg_am_mapped(am, eu, mmu_idx); in get_seg_physical_address()
118 MMUAccessType access_type, int mmu_idx) in get_physical_address() argument
122 int user_mode = mmu_idx == MIPS_HFLAG_UM; in get_physical_address()
123 int supervisor_mode = mmu_idx == MIPS_HFLAG_SM; in get_physical_address()
144 mmu_idx, segctl, 0x3FFFFFFF); in get_physical_address()
208 access_type, mmu_idx, in get_physical_address()
213 access_type, mmu_idx, in get_physical_address()
218 access_type, mmu_idx, in get_physical_address()
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/openbmc/qemu/target/ppc/
H A Dmem_helper.c58 MMUAccessType access_type, int mmu_idx, in probe_contiguous() argument
86 int mmu_idx = ppc_env_mmu_index(env, false); in helper_lmw() local
88 MMU_DATA_LOAD, mmu_idx, raddr); in helper_lmw()
108 int mmu_idx = ppc_env_mmu_index(env, false); in helper_stmw() local
110 MMU_DATA_STORE, mmu_idx, raddr); in helper_stmw()
130 int mmu_idx; in do_lsw() local
138 mmu_idx = ppc_env_mmu_index(env, false); in do_lsw()
219 int mmu_idx; in helper_stsw() local
227 mmu_idx = ppc_env_mmu_index(env, false); in helper_stsw()
289 haddr = tlb_vaddr_to_host(env, addr, MMU_DATA_STORE, mmu_idx); in dcbz_common()
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H A Dmmu-booke.c261 static bool is_epid_mmu(int mmu_idx) in is_epid_mmu() argument
263 return mmu_idx == PPC_TLB_EPID_STORE || mmu_idx == PPC_TLB_EPID_LOAD; in is_epid_mmu()
272 if (is_epid_mmu(mmu_idx)) { in mmubooke206_esr()
287 int mmu_idx, uint32_t *epid_out, in mmubooke206_get_as() argument
290 if (is_epid_mmu(mmu_idx)) { in mmubooke206_get_as()
292 if (mmu_idx == PPC_TLB_EPID_STORE) { in mmubooke206_get_as()
316 bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr); in mmubooke206_check_tlb()
393 int mmu_idx) in mmubooke206_get_physical_address() argument
406 access_type, mmu_idx); in mmubooke206_get_physical_address()
428 bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr); in booke206_update_mas_tlb_miss()
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H A Dmmu-radix64.c235 int mmu_idx, bool partition_scoped) in ppc_radix64_check_prot() argument
253 } else if (mmuidx_pr(mmu_idx) || (pte & R_PTE_EAA_PRIV) || in ppc_radix64_check_prot()
450 eaddr, mmu_idx, g_raddr); in ppc_radix64_partition_scoped_xlate()
529 eaddr, mmu_idx, pid); in ppc_radix64_process_scoped_xlate()
642 g_prot, mmu_idx, false)) { in ppc_radix64_process_scoped_xlate()
690 assert(!(mmuidx_hv(mmu_idx) && cpu->vhyp)); in ppc_radix64_xlate_impl()
692 relocation = !mmuidx_real(mmu_idx); in ppc_radix64_xlate_impl()
700 if (mmuidx_hv(mmu_idx) || !env->has_hv_mode) { in ppc_radix64_xlate_impl()
787 if (lpid || !mmuidx_hv(mmu_idx)) { in ppc_radix64_xlate_impl()
793 mmu_idx, lpid, in ppc_radix64_xlate_impl()
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H A Dmmu-hash32.c40 static target_ulong hash32_bat_size(int mmu_idx, in hash32_bat_size() argument
43 if ((mmuidx_pr(mmu_idx) && !(batu & BATU32_VP)) in hash32_bat_size()
44 || (!mmuidx_pr(mmu_idx) && !(batu & BATU32_VS))) { in hash32_bat_size()
53 int mmu_idx) in ppc_hash32_bat_lookup() argument
74 mask = hash32_bat_size(mmu_idx, batu, batl); in ppc_hash32_bat_lookup()
116 hwaddr *raddr, int *prot, int mmu_idx, in ppc_hash32_direct_store() argument
181 if (ppc_hash32_key(mmuidx_pr(mmu_idx), sr)) { in ppc_hash32_direct_store()
295 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx, in ppc_hash32_xlate() argument
310 if (mmuidx_real(mmu_idx)) { in ppc_hash32_xlate()
350 raddrp, protp, mmu_idx, guest_visible); in ppc_hash32_xlate()
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H A Dmmu-hash64.c398 static int ppc_hash64_pte_prot(int mmu_idx, in ppc_hash64_pte_prot() argument
408 key = !!(mmuidx_pr(mmu_idx) ? (slb->vsid & SLB_VSID_KP) in ppc_hash64_pte_prot()
826 if (!mmuidx_real(mmu_idx)) { in ppc_hash64_set_isi()
831 if (vpm && !mmuidx_hv(mmu_idx)) { in ppc_hash64_set_isi()
846 if (!mmuidx_real(mmu_idx)) { in ppc_hash64_set_dsi()
851 if (vpm && !mmuidx_hv(mmu_idx)) { in ppc_hash64_set_dsi()
1006 if (mmuidx_real(mmu_idx)) { in ppc_hash64_xlate()
1018 } else if (mmuidx_hv(mmu_idx) || !env->has_hv_mode) { in ppc_hash64_xlate()
1052 ppc_hash64_set_dsi(cs, mmu_idx, 0, eaddr, in ppc_hash64_xlate()
1124 ppc_hash64_set_dsi(cs, mmu_idx, slb->vsid, eaddr, in ppc_hash64_xlate()
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/openbmc/qemu/target/arm/
H A Dptw.c130 switch (mmu_idx) { in stage_1_mmu_idx()
138 return mmu_idx; in stage_1_mmu_idx()
236 switch (mmu_idx) { in regime_translation_disabled()
1400 switch (mmu_idx) { in get_S1prot()
2039 switch (mmu_idx) { in get_phys_addr_lpae()
3217 switch (mmu_idx) { in get_phys_addr_disabled()
3411 switch (mmu_idx) { in get_phys_addr_nogpc()
3555 .in_mmu_idx = mmu_idx, in get_phys_addr_with_space_nogpc()
3566 .in_mmu_idx = mmu_idx, in get_phys_addr()
3570 switch (mmu_idx) { in get_phys_addr()
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H A Dinternals.h799 return mmu_idx | ARM_MMU_IDX_M; in core_to_arm_mmu_idx()
801 return mmu_idx | ARM_MMU_IDX_A; in core_to_arm_mmu_idx()
808 return mmu_idx | ARM_MMU_IDX_A; in core_to_aa64_mmu_idx()
867 switch (mmu_idx) { in regime_has_2_ranges()
885 switch (mmu_idx) { in regime_is_pan()
898 return mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S; in regime_is_stage2()
904 switch (mmu_idx) { in regime_el()
938 switch (mmu_idx) { in regime_is_user()
972 if (mmu_idx == ARMMMUIdx_Stage2) { in regime_tcr()
994 int el = regime_el(env, mmu_idx); in regime_using_lpae_format()
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/openbmc/qemu/target/i386/tcg/
H A Daccess.c13 MMUAccessType type, int mmu_idx, uintptr_t ra) in access_prepare_mmu() argument
27 ret->mmu_idx = mmu_idx; in access_prepare_mmu()
31 haddr1 = probe_access(env, vaddr, size1, type, mmu_idx, ra); in access_prepare_mmu()
51 int mmu_idx = cpu_mmu_index(env_cpu(env), false); in access_prepare() local
52 access_prepare_mmu(ret, env, vaddr, size, type, mmu_idx, ra); in access_prepare()
93 return cpu_ldub_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); in access_ldb()
103 return cpu_lduw_le_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); in access_ldw()
113 return cpu_ldl_le_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); in access_ldl()
123 return cpu_ldq_le_mmuidx_ra(ac->env, addr, ac->mmu_idx, ac->ra); in access_ldq()
133 cpu_stb_mmuidx_ra(ac->env, addr, val, ac->mmu_idx, ac->ra); in access_stb()
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/openbmc/qemu/target/sparc/
H A Dmmu_helper.c70 int rw, int mmu_idx) in get_physical_address() argument
80 is_user = mmu_idx == MMU_USER_IDX; in get_physical_address()
82 if (mmu_idx == MMU_PHYS_IDX) { in get_physical_address()
232 tlb_set_page_full(cs, mmu_idx, vaddr, &full); in sparc_cpu_tlb_fill()
248 tlb_set_page_full(cs, mmu_idx, vaddr, &full); in sparc_cpu_tlb_fill()
506 switch (mmu_idx) { in build_sfsr()
553 sfsr = build_sfsr(env, mmu_idx, rw); in get_physical_address_data()
555 switch (mmu_idx) { in get_physical_address_data()
652 switch (mmu_idx) { in get_physical_address_code()
743 if (mmu_idx == MMU_PHYS_IDX) { in get_physical_address()
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H A Dtrace-events4 …uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DFAULT at 0x%"PRIx64" context 0x%"P…
5 …(uint64_t address, uint64_t context, int mmu_idx, uint32_t tl) "DPROT at 0x%"PRIx64" context 0x%"P…
9 …_phys_addr_code(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t ad…
10 …_phys_addr_data(uint32_t tl, int mmu_idx, uint64_t prim_context, uint64_t sec_context, uint64_t ad…
11 …nt64_t paddr, int mmu_idx, uint32_t tl, uint64_t prim_context, uint64_t sec_context) "Translate at…
/openbmc/qemu/target/riscv/
H A Dop_helper.c158 int mmu_idx = riscv_env_mmu_index(env, false); in helper_cbo_zero() local
206 int mmu_idx = riscv_env_mmu_index(env, false); in check_zicbom_access() local
239 probe_write(env, address, cbomlen, mmu_idx, ra); in check_zicbom_access()
456 MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); in helper_hyp_hlv_bu()
465 MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); in helper_hyp_hlv_hu()
474 MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); in helper_hyp_hlv_wu()
483 MemOpIdx oi = make_memop_idx(MO_TEUQ, mmu_idx); in helper_hyp_hlv_d()
492 MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx); in helper_hyp_hsv_b()
501 MemOpIdx oi = make_memop_idx(MO_TEUW, mmu_idx); in helper_hyp_hsv_h()
510 MemOpIdx oi = make_memop_idx(MO_TEUL, mmu_idx); in helper_hyp_hsv_w()
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H A Dinternals.h40 static inline int mmuidx_priv(int mmu_idx) in mmuidx_priv() argument
42 int ret = mmu_idx & 3; in mmuidx_priv()
49 static inline bool mmuidx_sum(int mmu_idx) in mmuidx_sum() argument
51 return (mmu_idx & 3) == MMUIdx_S_SUM; in mmuidx_sum()
54 static inline bool mmuidx_2stage(int mmu_idx) in mmuidx_2stage() argument
56 return mmu_idx & MMU_2STAGE_BIT; in mmuidx_2stage()
/openbmc/qemu/target/i386/tcg/sysemu/
H A Dsvm_helper.c42 mmu_idx, 0); in svm_save_seg()
62 mmu_idx, 0); in svm_load_seg()
65 mmu_idx, 0); in svm_load_seg()
68 mmu_idx, 0); in svm_load_seg()
71 mmu_idx, 0); in svm_load_seg()
479 int mmu_idx = MMU_PHYS_IDX; in helper_vmload() local
496 mmu_idx = MMU_NESTED_IDX; in helper_vmload()
503 svm_load_seg(env, mmu_idx, in helper_vmload()
505 svm_load_seg(env, mmu_idx, in helper_vmload()
540 int mmu_idx = MMU_PHYS_IDX; in helper_vmsave() local
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/openbmc/qemu/include/exec/
H A Dexec-all.h207 void tlb_set_page_full(CPUState *cpu, int mmu_idx, vaddr addr,
234 int prot, int mmu_idx, vaddr size);
243 int mmu_idx, vaddr size);
325 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr);
328 int mmu_idx, uintptr_t retaddr) in probe_write() argument
330 return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); in probe_write()
334 int mmu_idx, uintptr_t retaddr) in probe_read() argument
336 return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); in probe_read()
359 MMUAccessType access_type, int mmu_idx,
373 MMUAccessType access_type, int mmu_idx,
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H A Dcpu_ldst.h169 int mmu_idx, uintptr_t ra);
171 int mmu_idx, uintptr_t ra);
175 int mmu_idx, uintptr_t ra);
183 int mmu_idx, uintptr_t ra);
190 int mmu_idx, uintptr_t ra);
192 int mmu_idx, uintptr_t ra);
194 int mmu_idx, uintptr_t ra);
196 int mmu_idx, uintptr_t ra);
198 int mmu_idx, uintptr_t ra);
200 int mmu_idx, uintptr_t ra);
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/openbmc/qemu/target/microblaze/
H A Dhelper.c40 MMUAccessType access_type, int mmu_idx, in mb_cpu_tlb_fill() argument
52 if (mmu_idx == MMU_NOMMU_IDX) { in mb_cpu_tlb_fill()
56 tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, in mb_cpu_tlb_fill()
61 hit = mmu_translate(cpu, &lu, address, access_type, mmu_idx); in mb_cpu_tlb_fill()
67 mmu_idx, vaddr, paddr, lu.prot); in mb_cpu_tlb_fill()
68 tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, in mb_cpu_tlb_fill()
79 mmu_idx, address); in mb_cpu_tlb_fill()
234 int mmu_idx = cpu_mmu_index(cs, false); in mb_cpu_get_phys_page_attrs_debug() local
241 if (mmu_idx != MMU_NOMMU_IDX) { in mb_cpu_get_phys_page_attrs_debug()
273 int mmu_idx, uintptr_t retaddr) in mb_cpu_do_unaligned_access() argument
/openbmc/qemu/target/loongarch/
H A Dcpu_helper.c17 int access_type, int index, int mmu_idx) in loongarch_map_tlb_entry() argument
20 uint64_t plv = mmu_idx; in loongarch_map_tlb_entry()
146 MMUAccessType access_type, int mmu_idx) in loongarch_map_address() argument
153 address, access_type, index, mmu_idx); in loongarch_map_address()
161 MMUAccessType access_type, int mmu_idx) in loongarch_map_address() argument
181 MMUAccessType access_type, int mmu_idx) in get_physical_address() argument
183 int user_mode = mmu_idx == MMU_USER_IDX; in get_physical_address()
184 int kernel_mode = mmu_idx == MMU_KERNEL_IDX; in get_physical_address()
225 access_type, mmu_idx); in get_physical_address()
/openbmc/qemu/target/hppa/
H A Dmem_helper.c208 if (MMU_IDX_MMU_DISABLED(mmu_idx)) { in hppa_get_physical_address()
209 switch (mmu_idx) { in hppa_get_physical_address()
240 priv = MMU_IDX_TO_PRIV(mmu_idx); in hppa_get_physical_address()
271 if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { in hppa_get_physical_address()
335 int prot, excp, mmu_idx; in hppa_cpu_get_phys_page_debug() local
340 mmu_idx = (cpu->env.psw & PSW_D ? MMU_KERNEL_IDX : in hppa_cpu_get_phys_page_debug()
416 MMU_IDX_MMU_DISABLED(mmu_idx)); in hppa_cpu_do_transaction_failed()
421 MMUAccessType type, int mmu_idx, in hppa_cpu_tlb_fill() argument
464 prot, mmu_idx, TARGET_PAGE_SIZE); in hppa_cpu_tlb_fill()
703 int mmu_idx = cpu_mmu_index(env_cpu(env), 0); in HELPER() local
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