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Searched refs:mmVCE_VCPU_CACHE_OFFSET1 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h57 #define mmVCE_VCPU_CACHE_OFFSET1 0x800B macro
H A Dvce_2_0_d.h31 #define mmVCE_VCPU_CACHE_OFFSET1 0x800b macro
H A Dvce_3_0_d.h31 #define mmVCE_VCPU_CACHE_OFFSET1 0x800b macro
H A Dvce_4_0_offset.h36 #define mmVCE_VCPU_CACHE_OFFSET1 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v3_0.c582 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); in vce_v3_0_mc_resume()
591 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff); in vce_v3_0_mc_resume()
H A Dvce_v2_0.c192 WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff); in vce_v2_0_mc_resume()
H A Dvce_v4_0.c289 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), in vce_v4_0_sriov_start()
676 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_VCPU_CACHE_OFFSET1), (offset & ~0x0f000000) | (1 << 24)); in vce_v4_0_mc_resume()