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Searched refs:mmVCE_SYS_INT_EN (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h51 #define mmVCE_SYS_INT_EN 0x8340 macro
H A Dvce_2_0_d.h53 #define mmVCE_SYS_INT_EN 0x84c0 macro
H A Dvce_3_0_d.h58 #define mmVCE_SYS_INT_EN 0x8540 macro
H A Dvce_4_0_offset.h106 #define mmVCE_SYS_INT_EN … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v4_0.c300 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), in vce_v4_0_sriov_start()
687 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), in vce_v4_0_mc_resume()
1054 WREG32_P(SOC15_REG_OFFSET(VCE, 0, mmVCE_SYS_INT_EN), val, in vce_v4_0_set_interrupt_state()
H A Dvce_v2_0.c557 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); in vce_v2_0_set_interrupt_state()
H A Dvce_v3_0.c739 WREG32_P(mmVCE_SYS_INT_EN, val, ~VCE_SYS_INT_EN__VCE_SYS_INT_TRAP_INTERRUPT_EN_MASK); in vce_v3_0_set_interrupt_state()