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Searched refs:mmVCE_CLOCK_GATING_B (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvce_v2_0.c162 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_init_cg()
165 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_init_cg()
175 WREG32(mmVCE_CLOCK_GATING_B, 0xf7); in vce_v2_0_mc_resume()
315 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
317 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
329 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_set_sw_cg()
332 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_sw_cg()
352 tmp = RREG32(mmVCE_CLOCK_GATING_B); in vce_v2_0_set_dyn_cg()
358 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
362 WREG32(mmVCE_CLOCK_GATING_B, tmp); in vce_v2_0_set_dyn_cg()
H A Dvce_v3_0.c182 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
185 WREG32(mmVCE_CLOCK_GATING_B, data); in vce_v3_0_set_vce_sw_clock_gating()
208 data = RREG32(mmVCE_CLOCK_GATING_B); in vce_v3_0_set_vce_sw_clock_gating()
211 WREG32(mmVCE_CLOCK_GATING_B, data); in vce_v3_0_set_vce_sw_clock_gating()
559 WREG32(mmVCE_CLOCK_GATING_B, 0x1FF); in vce_v3_0_mc_resume()
H A Dvce_v4_0.c643 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), 0x1FF); in vce_v4_0_mc_resume()
854 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));
857 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);
880 data = RREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B));
883 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_CLOCK_GATING_B), data);
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vce/
H A Dvce_1_0_d.h27 #define mmVCE_CLOCK_GATING_B 0x80BF macro
H A Dvce_2_0_d.h48 #define mmVCE_CLOCK_GATING_B 0x80bf macro
H A Dvce_3_0_d.h48 #define mmVCE_CLOCK_GATING_B 0x80bf macro
H A Dvce_4_0_offset.h94 #define mmVCE_CLOCK_GATING_B … macro