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Searched refs:mmUVD_VCPU_NONCACHE_SIZE0 (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_offset.h723 #define mmUVD_VCPU_NONCACHE_SIZE0 … macro
H A Dvcn_2_0_0_offset.h652 #define mmUVD_VCPU_NONCACHE_SIZE0 … macro
H A Dvcn_3_0_0_offset.h1099 #define mmUVD_VCPU_NONCACHE_SIZE0 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c381 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v2_0_mc_resume()
475 UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v2_0_mc_resume_dpg_mode()
H A Dvcn_v2_5.c464 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v2_5_mc_resume()
557 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v2_5_mc_resume_dpg_mode()
H A Dvcn_v3_0.c494 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_SIZE0, in vcn_v3_0_mc_resume()
586 VCN, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), in vcn_v3_0_mc_resume_dpg_mode()