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Searched refs:mmUVD_SYS_INT_EN (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h332 #define mmUVD_SYS_INT_EN … macro
H A Dvcn_2_5_offset.h535 #define mmUVD_SYS_INT_EN … macro
H A Dvcn_2_0_0_offset.h540 #define mmUVD_SYS_INT_EN … macro
H A Dvcn_3_0_0_offset.h865 #define mmUVD_SYS_INT_EN … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v1_0.c902 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN), in vcn_v1_0_start_spg_mode()
1065 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN, in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_5.c815 SOC15_DPG_MODE_OFFSET(VCN, 0, mmUVD_SYS_INT_EN), in vcn_v2_6_enable_ras()