Home
last modified time | relevance | path

Searched refs:mmUVD_RB_BASE_HI2 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h40 #define mmUVD_RB_BASE_HI2 0x3c22 macro
H A Duvd_7_0_offset.h86 #define mmUVD_RB_BASE_HI2 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h208 #define mmUVD_RB_BASE_HI2 … macro
H A Dvcn_2_5_offset.h563 #define mmUVD_RB_BASE_HI2 … macro
H A Dvcn_2_0_0_offset.h920 #define mmUVD_RB_BASE_HI2 … macro
H A Dvcn_3_0_0_offset.h893 #define mmUVD_RB_BASE_HI2 … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c1096 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
H A Dvcn_v1_0.c955 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1255 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
H A Dvcn_v2_5.c1148 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1498 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
H A Dvcn_v3_0.c1273 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1648 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
H A Duvd_v6_0.c873 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
H A Duvd_v7_0.c1124 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()