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Searched refs:mmUVD_RB_BASE_HI (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_6_0_d.h45 #define mmUVD_RB_BASE_HI 0x3c27 macro
H A Duvd_7_0_offset.h96 #define mmUVD_RB_BASE_HI … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h218 #define mmUVD_RB_BASE_HI … macro
H A Dvcn_2_5_offset.h553 #define mmUVD_RB_BASE_HI … macro
H A Dvcn_2_0_0_offset.h930 #define mmUVD_RB_BASE_HI … macro
H A Dvcn_3_0_0_offset.h883 #define mmUVD_RB_BASE_HI … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c1087 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1239 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
1956 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), in vcn_v2_0_start_sriov()
H A Dvcn_v2_5.c1139 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1312 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI), in vcn_v2_5_sriov_start()
1488 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
H A Dvcn_v3_0.c1264 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1399 mmUVD_RB_BASE_HI), in vcn_v3_0_start_sriov()
1638 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
H A Duvd_v7_0.c922 …MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_ad… in uvd_v7_0_sriov_start()
1117 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()
H A Dvcn_v1_0.c948 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1248 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
H A Duvd_v6_0.c866 WREG32(mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()