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Searched refs:mmUVD_MPC_SET_MUXA0_BASE_IDX (Results 1 – 5 of 5) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h167 #define mmUVD_MPC_SET_MUXA0_BASE_IDX … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h347 #define mmUVD_MPC_SET_MUXA0_BASE_IDX … macro
H A Dvcn_2_5_offset.h762 #define mmUVD_MPC_SET_MUXA0_BASE_IDX … macro
H A Dvcn_2_0_0_offset.h597 #define mmUVD_MPC_SET_MUXA0_BASE_IDX … macro
H A Dvcn_3_0_0_offset.h1142 #define mmUVD_MPC_SET_MUXA0_BASE_IDX … macro