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Searched refs:mmUVD_MPC_SET_ALU (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h59 #define mmUVD_MPC_SET_ALU 0x3d7e macro
H A Duvd_4_0_d.h54 #define mmUVD_MPC_SET_ALU 0x3D7E macro
H A Duvd_3_1_d.h61 #define mmUVD_MPC_SET_ALU 0x3d7e macro
H A Duvd_5_0_d.h65 #define mmUVD_MPC_SET_ALU 0x3d7e macro
H A Duvd_6_0_d.h81 #define mmUVD_MPC_SET_ALU 0x3d7e macro
H A Duvd_7_0_offset.h176 #define mmUVD_MPC_SET_ALU … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h356 #define mmUVD_MPC_SET_ALU … macro
H A Dvcn_2_5_offset.h771 #define mmUVD_MPC_SET_ALU … macro
H A Dvcn_2_0_0_offset.h606 #define mmUVD_MPC_SET_ALU … macro
H A Dvcn_3_0_0_offset.h1151 #define mmUVD_MPC_SET_ALU … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c321 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v4_2_start()
H A Duvd_v3_1.c365 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v3_1_start()
H A Duvd_v5_0.c367 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v5_0_start()
H A Duvd_v6_0.c781 WREG32(mmUVD_MPC_SET_ALU, 0); in uvd_v6_0_start()
H A Duvd_v7_0.c1023 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0); in uvd_v7_0_start()