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Searched refs:mmUVD_MPC_CNTL (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h53 #define mmUVD_MPC_CNTL 0x3d77 macro
H A Duvd_4_0_d.h53 #define mmUVD_MPC_CNTL 0x3D77 macro
H A Duvd_3_1_d.h55 #define mmUVD_MPC_CNTL 0x3d77 macro
H A Duvd_5_0_d.h59 #define mmUVD_MPC_CNTL 0x3d77 macro
H A Duvd_6_0_d.h75 #define mmUVD_MPC_CNTL 0x3d77 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h344 #define mmUVD_MPC_CNTL … macro
H A Dvcn_2_5_offset.h757 #define mmUVD_MPC_CNTL … macro
H A Dvcn_2_0_0_offset.h592 #define mmUVD_MPC_CNTL … macro
H A Dvcn_3_0_0_offset.h1137 #define mmUVD_MPC_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c314 tmp = RREG32(mmUVD_MPC_CNTL); in uvd_v4_2_start()
315 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); in uvd_v4_2_start()
H A Duvd_v3_1.c358 tmp = RREG32(mmUVD_MPC_CNTL); in uvd_v3_1_start()
359 WREG32(mmUVD_MPC_CNTL, tmp | 0x10); in uvd_v3_1_start()
H A Dvcn_v2_0.c839 UVD, 0, mmUVD_MPC_CNTL), in vcn_v2_0_start_dpg_mode()
970 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); in vcn_v2_0_start()
973 WREG32_SOC15(VCN, 0, mmUVD_MPC_CNTL, tmp); in vcn_v2_0_start()
H A Dvcn_v1_0.c825 tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL); in vcn_v1_0_start_spg_mode()
828 WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp); in vcn_v1_0_start_spg_mode()
1010 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL, in vcn_v1_0_start_dpg_mode()
H A Dvcn_v2_5.c864 VCN, 0, mmUVD_MPC_CNTL), in vcn_v2_5_start_dpg_mode()
1016 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v2_5_start()
1019 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v2_5_start()
H A Dvcn_v3_0.c987 VCN, inst_idx, mmUVD_MPC_CNTL), in vcn_v3_0_start_dpg_mode()
1149 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL); in vcn_v3_0_start()
1152 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp); in vcn_v3_0_start()