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Searched refs:mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_5_offset.h859 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH … macro
H A Dvcn_2_0_0_offset.h950 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH … macro
H A Dvcn_3_0_0_offset.h1277 #define mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c378 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v2_0_mc_resume()
470 UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v2_0_mc_resume_dpg_mode()
H A Dvcn_v2_5.c461 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v2_5_mc_resume()
552 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v2_5_mc_resume_dpg_mode()
H A Dvcn_v3_0.c491 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH, in vcn_v3_0_mc_resume()
581 VCN, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), in vcn_v3_0_mc_resume_dpg_mode()