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Searched refs:mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h74 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h164 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … macro
H A Dvcn_2_5_offset.h877 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … macro
H A Dvcn_2_0_0_offset.h832 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … macro
H A Dvcn_3_0_0_offset.h1363 #define mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c368 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
455 UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
1934 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
H A Dvcn_v2_5.c451 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
537 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
1290 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
H A Dvcn_v3_0.c481 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
566 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
1379 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
H A Duvd_v7_0.c709 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
852 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
H A Dvcn_v1_0.c339 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
411 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()