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Searched refs:mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_offset.h70 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h160 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
H A Dvcn_2_5_offset.h869 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
H A Dvcn_2_0_0_offset.h824 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
H A Dvcn_3_0_0_offset.h1355 #define mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v2_0.c360 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_0_mc_resume()
435 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_0_mc_resume_dpg_mode()
444 UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
1919 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_0_start_sriov()
H A Dvcn_v2_5.c443 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v2_5_mc_resume()
517 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_mc_resume_dpg_mode()
526 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
1276 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v2_5_sriov_start()
H A Dvcn_v3_0.c473 WREG32_SOC15(VCN, inst, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v3_0_mc_resume()
546 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v3_0_mc_resume_dpg_mode()
555 VCN, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v3_0_mc_resume_dpg_mode()
1364 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v3_0_start_sriov()
H A Duvd_v7_0.c702 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in uvd_v7_0_mc_resume()
845 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in uvd_v7_0_sriov_start()
H A Dvcn_v1_0.c331 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_spg_mode()
401 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v1_0_mc_resume_dpg_mode()