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Searched refs:mmUVD_CONTEXT_ID (Results 1 – 16 of 16) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h81 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_4_0_d.h38 #define mmUVD_CONTEXT_ID 0x3DBD macro
H A Duvd_3_1_d.h83 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_5_0_d.h87 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_6_0_d.h103 #define mmUVD_CONTEXT_ID 0x3dbd macro
H A Duvd_7_0_offset.h218 #define mmUVD_CONTEXT_ID … macro
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v4_2.c477 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_emit_fence()
508 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v4_2_ring_test_ring()
513 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v4_2_ring_test_ring()
517 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v4_2_ring_test_ring()
H A Duvd_v3_1.c115 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_emit_fence()
146 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v3_1_ring_test_ring()
151 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v3_1_ring_test_ring()
155 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v3_1_ring_test_ring()
H A Duvd_v5_0.c493 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_emit_fence()
524 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v5_0_ring_test_ring()
528 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v5_0_ring_test_ring()
532 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v5_0_ring_test_ring()
H A Duvd_v6_0.c924 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_emit_fence()
987 WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v6_0_ring_test_ring()
992 amdgpu_ring_write(ring, PACKET0(mmUVD_CONTEXT_ID, 0)); in uvd_v6_0_ring_test_ring()
996 tmp = RREG32(mmUVD_CONTEXT_ID); in uvd_v6_0_ring_test_ring()
H A Duvd_v7_0.c1185 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_emit_fence()
1255 WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD); in uvd_v7_0_ring_test_ring()
1261 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0)); in uvd_v7_0_ring_test_ring()
1265 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID); in uvd_v7_0_ring_test_ring()
H A Dvcn_v1_0.c1474 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0)); in vcn_v1_0_dec_ring_emit_fence()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h404 #define mmUVD_CONTEXT_ID … macro
H A Dvcn_2_5_offset.h545 #define mmUVD_CONTEXT_ID … macro
H A Dvcn_2_0_0_offset.h726 #define mmUVD_CONTEXT_ID … macro
H A Dvcn_3_0_0_offset.h875 #define mmUVD_CONTEXT_ID … macro