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Searched refs:mmUVD_CGC_CTRL (Results 1 – 19 of 19) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Duvd_v5_0.c679 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_set_sw_clock_gating()
718 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_set_sw_clock_gating()
773 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
776 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
782 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_enable_mgcg()
785 WREG32(mmUVD_CGC_CTRL, data); in uvd_v5_0_enable_mgcg()
850 data = RREG32(mmUVD_CGC_CTRL); in uvd_v5_0_get_clockgating_state()
H A Duvd_v4_2.c614 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
617 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
623 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_enable_mgcg()
626 WREG32(mmUVD_CGC_CTRL, data); in uvd_v4_2_enable_mgcg()
637 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v4_2_set_dcm()
653 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v4_2_set_dcm()
H A Duvd_v3_1.c213 tmp = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_set_dcm()
229 WREG32(mmUVD_CGC_CTRL, tmp); in uvd_v3_1_set_dcm()
607 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
610 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
616 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v3_1_enable_mgcg()
619 WREG32(mmUVD_CGC_CTRL, data); in uvd_v3_1_enable_mgcg()
H A Duvd_v6_0.c1336 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_set_sw_clock_gating()
1376 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_set_sw_clock_gating()
1433 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1436 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1442 orig = data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_enable_mgcg()
1445 WREG32(mmUVD_CGC_CTRL, data); in uvd_v6_0_enable_mgcg()
1515 data = RREG32(mmUVD_CGC_CTRL); in uvd_v6_0_get_clockgating_state()
H A Dvcn_v2_0.c498 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
505 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
530 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_disable_clock_gating()
551 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_disable_clock_gating()
628 UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_0_clock_gating_dpg_mode()
658 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
665 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
667 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v2_0_enable_clock_gating()
688 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v2_0_enable_clock_gating()
H A Dvcn_v1_0.c472 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
480 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
505 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_disable_clock_gating()
526 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_disable_clock_gating()
596 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
603 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
605 data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL); in vcn_v1_0_enable_clock_gating()
626 WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data); in vcn_v1_0_enable_clock_gating()
684 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel); in vcn_v1_0_clock_gating_dpg_mode()
H A Dvcn_v2_5.c581 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
588 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
616 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_disable_clock_gating()
637 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_disable_clock_gating()
715 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v2_5_clock_gating_dpg_mode()
746 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
753 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
755 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL); in vcn_v2_5_enable_clock_gating()
775 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data); in vcn_v2_5_enable_clock_gating()
H A Dvcn_v3_0.c703 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
710 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
738 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_disable_clock_gating()
759 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_disable_clock_gating()
859 VCN, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect); in vcn_v3_0_clock_gating_dpg_mode()
887 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
894 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
896 data = RREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL); in vcn_v3_0_enable_clock_gating()
917 WREG32_SOC15(VCN, inst, mmUVD_CGC_CTRL, data); in vcn_v3_0_enable_clock_gating()
H A Duvd_v7_0.c864 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL), in uvd_v7_0_sriov_start()
977 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0, in uvd_v7_0_start()
1615 data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1661 WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_4_2_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_4_0_d.h34 #define mmUVD_CGC_CTRL 0x3D2C macro
H A Duvd_3_1_d.h44 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_5_0_d.h50 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_6_0_d.h66 #define mmUVD_CGC_CTRL 0x3d2c macro
H A Duvd_7_0_offset.h146 #define mmUVD_CGC_CTRL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_offset.h308 #define mmUVD_CGC_CTRL … macro
H A Dvcn_2_5_offset.h501 #define mmUVD_CGC_CTRL … macro
H A Dvcn_2_0_0_offset.h508 #define mmUVD_CGC_CTRL … macro
H A Dvcn_3_0_0_offset.h817 #define mmUVD_CGC_CTRL … macro