Searched refs:mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU (Results 1 – 2 of 2) sorted by relevance
24 #define mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU 0x0d91 macro
49 mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU); in umc_v6_1_enable_umc_index_mode()64 mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU); in umc_v6_1_disable_umc_index_mode()79 mmRSMU_UMC_INDEX_REGISTER_NBIF_VG20_GPU); in umc_v6_1_get_umc_index_mode_state()