Searched refs:mmMP1_SMN_IH_SW_INT_CTRL (Results 1 – 7 of 7) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/ |
| H A D | mp_12_0_0_offset.h | 330 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_10_0_offset.h | 330 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_9_0_offset.h | 344 #define mmMP1_SMN_IH_SW_INT_CTRL 0x02c3 macro
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| H A D | mp_11_0_8_offset.h | 330 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_11_0_offset.h | 334 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
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| H A D | mp_11_5_0_offset.h | 378 #define mmMP1_SMN_IH_SW_INT_CTRL … macro
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| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | smu_v11_0.c | 1348 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); in smu_v11_0_set_irq_state()
1350 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); in smu_v11_0_set_irq_state()
1381 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); in smu_v11_0_set_irq_state()
1383 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val); in smu_v11_0_set_irq_state()
1436 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL); in smu_v11_0_irq_process()
1438 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data); in smu_v11_0_irq_process()
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