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Searched refs:mmMP1_SMN_IH_SW_INT (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/mp/
H A Dmp_12_0_0_offset.h328 #define mmMP1_SMN_IH_SW_INT … macro
H A Dmp_10_0_offset.h328 #define mmMP1_SMN_IH_SW_INT … macro
H A Dmp_9_0_offset.h342 #define mmMP1_SMN_IH_SW_INT 0x02c2 macro
H A Dmp_11_0_8_offset.h328 #define mmMP1_SMN_IH_SW_INT … macro
H A Dmp_11_0_offset.h332 #define mmMP1_SMN_IH_SW_INT … macro
H A Dmp_11_5_0_offset.h376 #define mmMP1_SMN_IH_SW_INT … macro
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c1376 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT); in smu_v11_0_set_irq_state()
1379 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val); in smu_v11_0_set_irq_state()