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Searched refs:mmMCIF_WRITE_COMBINE_CONTROL (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3968 #define mmMCIF_WRITE_COMBINE_CONTROL 0x0315 macro
H A Ddce_8_0_d.h1207 #define mmMCIF_WRITE_COMBINE_CONTROL 0x315 macro
H A Ddce_10_0_d.h1501 #define mmMCIF_WRITE_COMBINE_CONTROL 0x30d macro
H A Ddce_11_0_d.h1318 #define mmMCIF_WRITE_COMBINE_CONTROL 0x30d macro
H A Ddce_11_2_d.h1396 #define mmMCIF_WRITE_COMBINE_CONTROL 0x30d macro
H A Ddce_12_0_offset.h1016 #define mmMCIF_WRITE_COMBINE_CONTROL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h959 #define mmMCIF_WRITE_COMBINE_CONTROL … macro
H A Ddcn_3_0_1_offset.h1160 #define mmMCIF_WRITE_COMBINE_CONTROL … macro
H A Ddcn_2_1_0_offset.h1206 #define mmMCIF_WRITE_COMBINE_CONTROL … macro
H A Ddcn_1_0_offset.h1600 #define mmMCIF_WRITE_COMBINE_CONTROL … macro
H A Ddcn_3_0_2_offset.h1132 #define mmMCIF_WRITE_COMBINE_CONTROL … macro
H A Ddcn_2_0_0_offset.h1244 #define mmMCIF_WRITE_COMBINE_CONTROL … macro
H A Ddcn_3_0_0_offset.h1146 #define mmMCIF_WRITE_COMBINE_CONTROL … macro