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Searched refs:mmLVTMA_PWRSEQ_REF_DIV (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3953 #define mmLVTMA_PWRSEQ_REF_DIV 0x191B macro
H A Ddce_8_0_d.h1283 #define mmLVTMA_PWRSEQ_REF_DIV 0x191b macro
H A Ddce_10_0_d.h1570 #define mmLVTMA_PWRSEQ_REF_DIV 0x481d macro
H A Ddce_11_0_d.h1395 #define mmLVTMA_PWRSEQ_REF_DIV 0x481d macro
H A Ddce_11_2_d.h1475 #define mmLVTMA_PWRSEQ_REF_DIV 0x481d macro
H A Ddce_12_0_offset.h1854 #define mmLVTMA_PWRSEQ_REF_DIV … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h5475 #define mmLVTMA_PWRSEQ_REF_DIV … macro
H A Ddcn_2_1_0_offset.h11355 #define mmLVTMA_PWRSEQ_REF_DIV … macro
H A Ddcn_1_0_offset.h10397 #define mmLVTMA_PWRSEQ_REF_DIV … macro
H A Ddcn_3_0_2_offset.h11435 #define mmLVTMA_PWRSEQ_REF_DIV … macro
H A Ddcn_2_0_0_offset.h12772 #define mmLVTMA_PWRSEQ_REF_DIV … macro
H A Ddcn_3_0_0_offset.h12583 #define mmLVTMA_PWRSEQ_REF_DIV … macro