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Searched refs:mmLVTMA_PWRSEQ_CNTL (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3950 #define mmLVTMA_PWRSEQ_CNTL 0x1919 macro
H A Ddce_8_0_d.h1281 #define mmLVTMA_PWRSEQ_CNTL 0x1919 macro
H A Ddce_10_0_d.h1568 #define mmLVTMA_PWRSEQ_CNTL 0x481b macro
H A Ddce_11_0_d.h1393 #define mmLVTMA_PWRSEQ_CNTL 0x481b macro
H A Ddce_11_2_d.h1473 #define mmLVTMA_PWRSEQ_CNTL 0x481b macro
H A Ddce_12_0_offset.h1850 #define mmLVTMA_PWRSEQ_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h5471 #define mmLVTMA_PWRSEQ_CNTL … macro
H A Ddcn_1_0_offset.h10393 #define mmLVTMA_PWRSEQ_CNTL … macro
H A Ddcn_2_1_0_offset.h11351 #define mmLVTMA_PWRSEQ_CNTL … macro
H A Ddcn_3_0_2_offset.h11431 #define mmLVTMA_PWRSEQ_CNTL … macro
H A Ddcn_2_0_0_offset.h12768 #define mmLVTMA_PWRSEQ_CNTL … macro
H A Ddcn_3_0_0_offset.h12579 #define mmLVTMA_PWRSEQ_CNTL … macro