Home
last modified time | relevance | path

Searched refs:mmHDMI_ACR_48_0 (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v6_0.c1439 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v6_0_audio_set_acr()
1441 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v6_0_audio_set_acr()
H A Ddce_v10_0.c1502 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v10_0_afmt_update_ACR()
1504 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v10_0_afmt_update_ACR()
H A Ddce_v11_0.c1551 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset); in dce_v11_0_afmt_update_ACR()
1553 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp); in dce_v11_0_afmt_update_ACR()
H A Ddce_v8_0.c1461 WREG32(mmHDMI_ACR_48_0 + offset, (acr.cts_48khz << HDMI_ACR_48_0__HDMI_ACR_CTS_48__SHIFT)); in dce_v8_0_afmt_update_ACR()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3854 #define mmHDMI_ACR_48_0 0x1C3B macro
H A Ddce_8_0_d.h3215 #define mmHDMI_ACR_48_0 0x1c3b macro
H A Ddce_10_0_d.h3994 #define mmHDMI_ACR_48_0 0x4a32 macro
H A Ddce_11_0_d.h3867 #define mmHDMI_ACR_48_0 0x4a32 macro
H A Ddce_11_2_d.h5098 #define mmHDMI_ACR_48_0 0x4a32 macro