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Searched refs:mmDPG_PIPE_URGENCY_CONTROL (Results 1 – 9 of 9) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v10_0.c1125 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1128 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
1132 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v10_0_program_watermarks()
1135 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v10_0_program_watermarks()
H A Ddce_v11_0.c1157 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1160 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
1164 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset); in dce_v11_0_program_watermarks()
1167 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp); in dce_v11_0_program_watermarks()
H A Ddce_v8_0.c1066 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_program_watermarks()
1074 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v8_0_program_watermarks()
H A Ddce_v6_0.c965 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
973 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, in dce_v6_0_program_watermarks()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3556 #define mmDPG_PIPE_URGENCY_CONTROL 0x1B33 macro
H A Ddce_8_0_d.h5187 #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 macro
H A Ddce_10_0_d.h6401 #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 macro
H A Ddce_11_0_d.h6523 #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 macro
H A Ddce_11_2_d.h7821 #define mmDPG_PIPE_URGENCY_CONTROL 0x1b33 macro