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Searched refs:mmDP5_DP_VID_TIMING (Results 1 – 10 of 10) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3426 #define mmDP5_DP_VID_TIMING 0x4BC9 macro
H A Ddce_8_0_d.h3817 #define mmDP5_DP_VID_TIMING 0x4bc9 macro
H A Ddce_10_0_d.h4449 #define mmDP5_DP_VID_TIMING 0x4fa8 macro
H A Ddce_11_0_d.h4413 #define mmDP5_DP_VID_TIMING 0x4fa8 macro
H A Ddce_11_2_d.h5645 #define mmDP5_DP_VID_TIMING 0x4fa8 macro
H A Ddce_12_0_offset.h11630 #define mmDP5_DP_VID_TIMING … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9913 #define mmDP5_DP_VID_TIMING … macro
H A Ddcn_3_0_2_offset.h11255 #define mmDP5_DP_VID_TIMING … macro
H A Ddcn_2_0_0_offset.h12600 #define mmDP5_DP_VID_TIMING … macro
H A Ddcn_3_0_0_offset.h12399 #define mmDP5_DP_VID_TIMING … macro