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Searched refs:mmDP4_DP_DPHY_TRAINING_PATTERN_SEL (Results 1 – 11 of 11) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3337 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48D1 macro
H A Ddce_8_0_d.h3880 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x48d1 macro
H A Ddce_10_0_d.h4512 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 macro
H A Ddce_11_0_d.h4492 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 macro
H A Ddce_11_2_d.h5724 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x4eb0 macro
H A Ddce_12_0_offset.h11362 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h9619 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_2_1_0_offset.h11203 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_3_0_2_offset.h10935 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_2_0_0_offset.h12288 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_3_0_0_offset.h12071 #define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL … macro