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Searched refs:mmDP3_DP_SEC_CNTL1 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3307 #define mmDP3_DP_SEC_CNTL1 0x45AB macro
H A Ddce_8_0_d.h4015 #define mmDP3_DP_SEC_CNTL1 0x45ab macro
H A Ddce_10_0_d.h4647 #define mmDP3_DP_SEC_CNTL1 0x4dc4 macro
H A Ddce_11_0_d.h4680 #define mmDP3_DP_SEC_CNTL1 0x4dc4 macro
H A Ddce_11_2_d.h5912 #define mmDP3_DP_SEC_CNTL1 0x4dc4 macro
H A Ddce_12_0_offset.h11112 #define mmDP3_DP_SEC_CNTL1 … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h9000 #define mmDP3_DP_SEC_CNTL1 … macro
H A Ddcn_1_0_offset.h9339 #define mmDP3_DP_SEC_CNTL1 … macro
H A Ddcn_2_1_0_offset.h10903 #define mmDP3_DP_SEC_CNTL1 … macro
H A Ddcn_3_0_2_offset.h10622 #define mmDP3_DP_SEC_CNTL1 … macro
H A Ddcn_2_0_0_offset.h11990 #define mmDP3_DP_SEC_CNTL1 … macro
H A Ddcn_3_0_0_offset.h11758 #define mmDP3_DP_SEC_CNTL1 … macro