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Searched refs:mmDP3_DP_DPHY_8B10B_CNTL (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3272 #define mmDP3_DP_DPHY_8B10B_CNTL 0x45D3 macro
H A Ddce_8_0_d.h3911 #define mmDP3_DP_DPHY_8B10B_CNTL 0x45d3 macro
H A Ddce_10_0_d.h4543 #define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 macro
H A Ddce_11_0_d.h4531 #define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 macro
H A Ddce_11_2_d.h5763 #define mmDP3_DP_DPHY_8B10B_CNTL 0x4db4 macro
H A Ddce_12_0_offset.h11086 #define mmDP3_DP_DPHY_8B10B_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h8978 #define mmDP3_DP_DPHY_8B10B_CNTL … macro
H A Ddcn_1_0_offset.h9317 #define mmDP3_DP_DPHY_8B10B_CNTL … macro
H A Ddcn_2_1_0_offset.h10881 #define mmDP3_DP_DPHY_8B10B_CNTL … macro
H A Ddcn_3_0_2_offset.h10600 #define mmDP3_DP_DPHY_8B10B_CNTL … macro
H A Ddcn_2_0_0_offset.h11968 #define mmDP3_DP_DPHY_8B10B_CNTL … macro
H A Ddcn_3_0_0_offset.h11736 #define mmDP3_DP_DPHY_8B10B_CNTL … macro