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Searched refs:mmDP2_DP_DPHY_TRAINING_PATTERN_SEL (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3233 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42D1 macro
H A Ddce_8_0_d.h3878 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x42d1 macro
H A Ddce_10_0_d.h4510 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 macro
H A Ddce_11_0_d.h4490 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 macro
H A Ddce_11_2_d.h5722 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x4cb0 macro
H A Ddce_12_0_offset.h10794 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h8630 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_2_1_0_offset.h10543 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_1_0_offset.h8999 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_3_0_2_offset.h10248 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_2_0_0_offset.h11632 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … macro
H A Ddcn_3_0_0_offset.h11384 #define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL … macro