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Searched refs:mmDP1_DP_MSE_SAT0 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3193 #define mmDP1_DP_MSE_SAT0 0x1FE4 macro
H A Ddce_8_0_d.h4117 #define mmDP1_DP_MSE_SAT0 0x1fe4 macro
H A Ddce_10_0_d.h4749 #define mmDP1_DP_MSE_SAT0 0x4bd2 macro
H A Ddce_11_0_d.h4808 #define mmDP1_DP_MSE_SAT0 0x4bd2 macro
H A Ddce_11_2_d.h6040 #define mmDP1_DP_MSE_SAT0 0x4bd2 macro
H A Ddce_12_0_offset.h10570 #define mmDP1_DP_MSE_SAT0 macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5870 #define mmDP1_DP_MSE_SAT0 macro
H A Ddcn_3_0_3_offset.h5379 #define mmDP1_DP_MSE_SAT0 macro
H A Ddcn_3_0_1_offset.h8346 #define mmDP1_DP_MSE_SAT0 macro
H A Ddcn_1_0_offset.h8745 #define mmDP1_DP_MSE_SAT0 macro
H A Ddcn_2_1_0_offset.h10269 #define mmDP1_DP_MSE_SAT0 macro
H A Ddcn_3_0_2_offset.h9961 #define mmDP1_DP_MSE_SAT0 macro
H A Ddcn_2_0_0_offset.h11360 #define mmDP1_DP_MSE_SAT0 macro
H A Ddcn_3_0_0_offset.h11097 #define mmDP1_DP_MSE_SAT0 macro