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Searched refs:mmDMCU_UC_CLK_GATING_CNTL (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h3038 #define mmDMCU_UC_CLK_GATING_CNTL 0x161B macro
H A Ddce_8_0_d.h3726 #define mmDMCU_UC_CLK_GATING_CNTL 0x161b macro
H A Ddce_10_0_d.h4351 #define mmDMCU_UC_CLK_GATING_CNTL 0x161b macro
H A Ddce_11_0_d.h4306 #define mmDMCU_UC_CLK_GATING_CNTL 0x161b macro
H A Ddce_11_2_d.h5538 #define mmDMCU_UC_CLK_GATING_CNTL 0x161b macro
H A Ddce_12_0_offset.h1280 #define mmDMCU_UC_CLK_GATING_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h375 #define mmDMCU_UC_CLK_GATING_CNTL … macro
H A Ddcn_3_0_1_offset.h570 #define mmDMCU_UC_CLK_GATING_CNTL … macro
H A Ddcn_1_0_offset.h1000 #define mmDMCU_UC_CLK_GATING_CNTL … macro
H A Ddcn_2_1_0_offset.h630 #define mmDMCU_UC_CLK_GATING_CNTL … macro
H A Ddcn_3_0_2_offset.h542 #define mmDMCU_UC_CLK_GATING_CNTL … macro
H A Ddcn_2_0_0_offset.h668 #define mmDMCU_UC_CLK_GATING_CNTL … macro
H A Ddcn_3_0_0_offset.h554 #define mmDMCU_UC_CLK_GATING_CNTL … macro