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Searched refs:mmDIG1_TMDS_DCBALANCER_CONTROL (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h2643 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1F84 macro
H A Ddce_8_0_d.h3465 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x1f84 macro
H A Ddce_10_0_d.h4244 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 macro
H A Ddce_11_0_d.h4189 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 macro
H A Ddce_11_2_d.h5420 #define mmDIG1_TMDS_DCBALANCER_CONTROL 0x4b73 macro
H A Ddce_12_0_offset.h10464 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5762 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_3_0_3_offset.h5274 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_3_0_1_offset.h8244 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_1_0_offset.h8641 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_2_1_0_offset.h10157 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_3_0_2_offset.h9856 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_2_0_0_offset.h11250 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro
H A Ddcn_3_0_0_offset.h10992 #define mmDIG1_TMDS_DCBALANCER_CONTROL … macro