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Searched refs:mmDIG0_TMDS_CTL0_1_GEN_CNTL (Results 1 – 13 of 13) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h2555 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1C86 macro
H A Ddce_8_0_d.h3472 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x1c86 macro
H A Ddce_10_0_d.h4251 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 macro
H A Ddce_11_0_d.h4198 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 macro
H A Ddce_11_2_d.h5429 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x4a75 macro
H A Ddce_12_0_offset.h10182 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5446 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro
H A Ddcn_3_0_3_offset.h4935 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro
H A Ddcn_1_0_offset.h8333 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro
H A Ddcn_2_1_0_offset.h9831 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro
H A Ddcn_3_0_2_offset.h9517 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro
H A Ddcn_2_0_0_offset.h10926 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro
H A Ddcn_3_0_0_offset.h10653 #define mmDIG0_TMDS_CTL0_1_GEN_CNTL … macro