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Searched refs:mmDC_I2C_SW_STATUS (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1337 #define mmDC_I2C_SW_STATUS 0x181C macro
H A Ddce_8_0_d.h3545 #define mmDC_I2C_SW_STATUS 0x181c macro
H A Ddce_10_0_d.h7159 #define mmDC_I2C_SW_STATUS 0x16d7 macro
H A Ddce_11_0_d.h7349 #define mmDC_I2C_SW_STATUS 0x16d7 macro
H A Ddce_11_2_d.h8741 #define mmDC_I2C_SW_STATUS 0x16d7 macro
H A Ddce_12_0_offset.h1642 #define mmDC_I2C_SW_STATUS … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5117 #define mmDC_I2C_SW_STATUS … macro
H A Ddcn_3_0_3_offset.h4557 #define mmDC_I2C_SW_STATUS … macro
H A Ddcn_3_0_1_offset.h7406 #define mmDC_I2C_SW_STATUS … macro
H A Ddcn_1_0_offset.h7673 #define mmDC_I2C_SW_STATUS … macro
H A Ddcn_2_1_0_offset.h9267 #define mmDC_I2C_SW_STATUS … macro
H A Ddcn_3_0_2_offset.h8953 #define mmDC_I2C_SW_STATUS … macro
H A Ddcn_2_0_0_offset.h10298 #define mmDC_I2C_SW_STATUS … macro
H A Ddcn_3_0_0_offset.h10027 #define mmDC_I2C_SW_STATUS … macro