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Searched refs:mmDC_I2C_DDC3_HW_STATUS (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1320 #define mmDC_I2C_DDC3_HW_STATUS 0x181F macro
H A Ddce_8_0_d.h3548 #define mmDC_I2C_DDC3_HW_STATUS 0x181f macro
H A Ddce_10_0_d.h7162 #define mmDC_I2C_DDC3_HW_STATUS 0x16da macro
H A Ddce_11_0_d.h7352 #define mmDC_I2C_DDC3_HW_STATUS 0x16da macro
H A Ddce_11_2_d.h8744 #define mmDC_I2C_DDC3_HW_STATUS 0x16da macro
H A Ddce_12_0_offset.h1648 #define mmDC_I2C_DDC3_HW_STATUS … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_1_offset.h7412 #define mmDC_I2C_DDC3_HW_STATUS … macro
H A Ddcn_1_0_offset.h7679 #define mmDC_I2C_DDC3_HW_STATUS … macro
H A Ddcn_2_1_0_offset.h9273 #define mmDC_I2C_DDC3_HW_STATUS … macro
H A Ddcn_3_0_2_offset.h8959 #define mmDC_I2C_DDC3_HW_STATUS … macro
H A Ddcn_2_0_0_offset.h10304 #define mmDC_I2C_DDC3_HW_STATUS … macro
H A Ddcn_3_0_0_offset.h10033 #define mmDC_I2C_DDC3_HW_STATUS … macro