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Searched refs:mmDC_I2C_DDC2_HW_STATUS (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1317 #define mmDC_I2C_DDC2_HW_STATUS 0x181E macro
H A Ddce_8_0_d.h3547 #define mmDC_I2C_DDC2_HW_STATUS 0x181e macro
H A Ddce_10_0_d.h7161 #define mmDC_I2C_DDC2_HW_STATUS 0x16d9 macro
H A Ddce_11_0_d.h7351 #define mmDC_I2C_DDC2_HW_STATUS 0x16d9 macro
H A Ddce_11_2_d.h8743 #define mmDC_I2C_DDC2_HW_STATUS 0x16d9 macro
H A Ddce_12_0_offset.h1646 #define mmDC_I2C_DDC2_HW_STATUS … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5121 #define mmDC_I2C_DDC2_HW_STATUS … macro
H A Ddcn_3_0_3_offset.h4561 #define mmDC_I2C_DDC2_HW_STATUS … macro
H A Ddcn_3_0_1_offset.h7410 #define mmDC_I2C_DDC2_HW_STATUS … macro
H A Ddcn_1_0_offset.h7677 #define mmDC_I2C_DDC2_HW_STATUS … macro
H A Ddcn_2_1_0_offset.h9271 #define mmDC_I2C_DDC2_HW_STATUS … macro
H A Ddcn_3_0_2_offset.h8957 #define mmDC_I2C_DDC2_HW_STATUS … macro
H A Ddcn_2_0_0_offset.h10302 #define mmDC_I2C_DDC2_HW_STATUS … macro
H A Ddcn_3_0_0_offset.h10031 #define mmDC_I2C_DDC2_HW_STATUS … macro