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Searched refs:mmDC_I2C_DDC1_HW_STATUS (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1314 #define mmDC_I2C_DDC1_HW_STATUS 0x181D macro
H A Ddce_8_0_d.h3546 #define mmDC_I2C_DDC1_HW_STATUS 0x181d macro
H A Ddce_10_0_d.h7160 #define mmDC_I2C_DDC1_HW_STATUS 0x16d8 macro
H A Ddce_11_0_d.h7350 #define mmDC_I2C_DDC1_HW_STATUS 0x16d8 macro
H A Ddce_11_2_d.h8742 #define mmDC_I2C_DDC1_HW_STATUS 0x16d8 macro
H A Ddce_12_0_offset.h1644 #define mmDC_I2C_DDC1_HW_STATUS … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h5119 #define mmDC_I2C_DDC1_HW_STATUS … macro
H A Ddcn_3_0_3_offset.h4559 #define mmDC_I2C_DDC1_HW_STATUS … macro
H A Ddcn_3_0_1_offset.h7408 #define mmDC_I2C_DDC1_HW_STATUS … macro
H A Ddcn_1_0_offset.h7675 #define mmDC_I2C_DDC1_HW_STATUS … macro
H A Ddcn_2_1_0_offset.h9269 #define mmDC_I2C_DDC1_HW_STATUS … macro
H A Ddcn_3_0_2_offset.h8955 #define mmDC_I2C_DDC1_HW_STATUS … macro
H A Ddcn_2_0_0_offset.h10300 #define mmDC_I2C_DDC1_HW_STATUS … macro
H A Ddcn_3_0_0_offset.h10029 #define mmDC_I2C_DDC1_HW_STATUS … macro