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Searched refs:mmCRTC_MASTER_UPDATE_MODE (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_hw_sequencer.c139 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), in dce112_enable_display_power_gating()
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
1701 value = dm_read_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE)); in dce110_timing_generator_enable_crtc_reset()
1708 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc_reset()
H A Ddce110_hw_sequencer.c236 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), in dce110_enable_display_power_gating()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v11_0.c2121 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); in dce_v11_0_crtc_do_set_base()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_11_0_d.h539 #define mmCRTC_MASTER_UPDATE_MODE 0x1bbe macro
H A Ddce_11_2_d.h546 #define mmCRTC_MASTER_UPDATE_MODE 0x1bbe macro