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Searched refs:mmCRTC_CONTROL (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c132 uint32_t addr2 = CRTC_REG(mmCRTC_CONTROL); in dce60_timing_generator_enable_advanced_request()
185 addr = CRTC_REG(mmCRTC_CONTROL); in dce60_is_tg_enabled()
H A Ddce60_resource.c114 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
138 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce100/
H A Ddce100_resource.c109 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
113 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
117 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
121 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
125 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
129 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce80/
H A Ddce80_resource.c114 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
120 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
132 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
138 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
144 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_resource.c119 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
123 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
127 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
131 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
139 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_resource.c118 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
122 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
126 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
130 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
134 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
138 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
H A Ddce110_timing_generator_v.c594 uint32_t address = mmCRTC_CONTROL; in dce110_timing_generator_v_set_early_control()
H A Ddce110_timing_generator.c111 uint32_t address = CRTC_REG(mmCRTC_CONTROL); in dce110_timing_generator_set_early_control()
2091 addr = CRTC_REG(mmCRTC_CONTROL); in dce110_is_tg_enabled()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Ddce_v8_0.c355 if (RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK) { in dce_v8_0_is_display_hung()
432 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v8_0_disable_dce()
436 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v8_0_disable_dce()
438 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v8_0_disable_dce()
H A Ddce_v10_0.c417 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_is_display_hung()
488 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v10_0_disable_dce()
492 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v10_0_disable_dce()
494 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v10_0_disable_dce()
H A Ddce_v11_0.c439 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_is_display_hung()
520 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]), in dce_v11_0_disable_dce()
524 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v11_0_disable_dce()
526 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v11_0_disable_dce()
H A Ddce_v6_0.c390 crtc_enabled = RREG32(mmCRTC_CONTROL + crtc_offsets[i]) & in dce_v6_0_disable_dce()
394 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]); in dce_v6_0_disable_dce()
396 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp); in dce_v6_0_disable_dce()
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h964 #define mmCRTC_CONTROL 0x1B9C macro
H A Ddce_8_0_d.h333 #define mmCRTC_CONTROL 0x1b9c macro
H A Ddce_10_0_d.h388 #define mmCRTC_CONTROL 0x1b9c macro
H A Ddce_11_0_d.h315 #define mmCRTC_CONTROL 0x1b9c macro
H A Ddce_11_2_d.h322 #define mmCRTC_CONTROL 0x1b9c macro