Home
last modified time | relevance | path

Searched refs:mmCPU_PLL_DIV_SEL_2 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/accel/habanalabs/include/goya/asic_reg/
H A Dcpu_pll_regs.h64 #define mmCPU_PLL_DIV_SEL_2 0x4A2288 macro
/openbmc/linux/drivers/accel/habanalabs/goya/
H A Dgoya.c1403 WREG32(mmCPU_PLL_DIV_SEL_2, 0x0); in goya_set_pll_refclk()