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Searched refs:mmBL1_PWM_FINAL_DUTY_CYCLE (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h470 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162C macro
H A Ddce_8_0_d.h55 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c macro
H A Ddce_10_0_d.h55 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c macro
H A Ddce_11_0_d.h51 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c macro
H A Ddce_11_2_d.h58 #define mmBL1_PWM_FINAL_DUTY_CYCLE 0x162c macro
H A Ddce_12_0_offset.h1310 #define mmBL1_PWM_FINAL_DUTY_CYCLE … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_offset.h7143 #define mmBL1_PWM_FINAL_DUTY_CYCLE … macro
H A Ddcn_2_0_0_offset.h8174 #define mmBL1_PWM_FINAL_DUTY_CYCLE … macro