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Searched refs:mmAZALIA_RIRB_AND_DP_CONTROL (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h435 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17C0 macro
H A Ddce_8_0_d.h5437 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17c0 macro
H A Ddce_10_0_d.h6678 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb macro
H A Ddce_11_0_d.h6840 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb macro
H A Ddce_11_2_d.h8185 #define mmAZALIA_RIRB_AND_DP_CONTROL 0x17eb macro
H A Ddce_12_0_offset.h1482 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_3_offset.h215 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
H A Ddcn_3_0_3_offset.h1163 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
H A Ddcn_3_0_1_offset.h1364 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
H A Ddcn_1_0_offset.h1804 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
H A Ddcn_2_1_0_offset.h1410 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
H A Ddcn_3_0_2_offset.h1336 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
H A Ddcn_2_0_0_offset.h1448 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro
H A Ddcn_3_0_0_offset.h1350 #define mmAZALIA_RIRB_AND_DP_CONTROL … macro