Searched refs:misc_mask (Results 1 – 5 of 5) sorted by relevance
39 u8 misc_mask; member49 return irq <= 7 ? &cpld_regs->pci_mask : &cpld_regs->misc_mask; in irq_to_pic_mask()113 &cpld_regs->misc_mask); in cpld_pic_cascade()185 out_8(&cpld_regs->misc_mask, ~(MISC_IGNORE)); in mpc5121_ads_cpld_pic_init()
901 if (misc_mask->inner_second_cvlan_tag || in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()902 misc_mask->inner_second_svlan_tag) { in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()904 misc_mask->inner_second_cvlan_tag = 0; in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()905 misc_mask->inner_second_svlan_tag = 0; in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()911 second_cfi, misc_mask, inner_second_cfi); in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()915 if (misc_mask->outer_second_cvlan_tag || in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()916 misc_mask->outer_second_svlan_tag) { in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()918 misc_mask->outer_second_cvlan_tag = 0; in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()919 misc_mask->outer_second_svlan_tag = 0; in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()925 second_cfi, misc_mask, outer_second_cfi); in dr_ste_v0_build_eth_l2_src_or_dst_bit_mask()[all …]
1275 if (misc_mask->inner_second_cvlan_tag || in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1276 misc_mask->inner_second_svlan_tag) { in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1278 misc_mask->inner_second_cvlan_tag = 0; in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1279 misc_mask->inner_second_svlan_tag = 0; in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1285 second_cfi, misc_mask, inner_second_cfi); in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1289 if (misc_mask->outer_second_cvlan_tag || in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1290 misc_mask->outer_second_svlan_tag) { in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1292 misc_mask->outer_second_cvlan_tag = 0; in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1293 misc_mask->outer_second_svlan_tag = 0; in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()1299 second_cfi, misc_mask, outer_second_cfi); in dr_ste_v1_build_eth_l2_src_or_dst_bit_mask()[all …]
370 u32 misc_mask; member
511 if (sigstruct->body.miscselect & sigstruct->body.misc_mask & in sgx_encl_init()