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Searched refs:mhartid (Results 1 – 10 of 10) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dtrace-events5 pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" P…
6 pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%"…
7 pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%…
8 pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write add…
10 mseccfg_csr_read(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": read mseccfg, val: 0x%" PRIx64
11 mseccfg_csr_write(uint64_t mhartid, uint64_t val) "hart %" PRIu64 ": write mseccfg, val: 0x%" PRIx64
H A Dpmp.c474 trace_pmpcfg_csr_write(env->mhartid, reg_index, val); in pmpcfg_csr_write()
503 trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); in pmpcfg_csr_read()
515 trace_pmpaddr_csr_write(env->mhartid, addr_index, val); in pmpaddr_csr_write()
563 trace_pmpaddr_csr_read(env->mhartid, addr_index, val); in pmpaddr_csr_read()
579 trace_mseccfg_csr_write(env->mhartid, val); in mseccfg_csr_write()
614 trace_mseccfg_csr_read(env->mhartid, env->mseccfg); in mseccfg_csr_read()
H A Dmachine.c414 VMSTATE_UINTTL(env.mhartid, RISCVCPU),
H A Dcpu.h261 target_ulong mhartid; member
H A Dcpu_helper.c1899 trace_riscv_trap(env->mhartid, async, cause, env->pc, tval, in riscv_cpu_do_interrupt()
1905 __func__, env->mhartid, async, cause, env->pc, tval, in riscv_cpu_do_interrupt()
H A Dcpu.c2740 return cpu->env.mhartid; in riscv_get_arch_id()
H A Dcsr.c1505 *val = env->mhartid; in read_mhartid()
/openbmc/linux/drivers/cache/
H A Dax45mp_cache.c70 int mhartid = smp_processor_id(); in ax45mp_cpu_cache_operation() local
78 writel(pa, base + AX45MP_L2C_REG_CN_ACC_OFFSET(mhartid)); in ax45mp_cpu_cache_operation()
79 writel(l2_op, base + AX45MP_L2C_REG_CN_CMD_OFFSET(mhartid)); in ax45mp_cpu_cache_operation()
81 AX45MP_CCTL_L2_STATUS_CN_MASK(mhartid)) != in ax45mp_cpu_cache_operation()
/openbmc/qemu/hw/riscv/
H A Driscv_hart.c50 s->harts[idx].env.mhartid = s->hartid_base + idx; in riscv_hart_realize()
/openbmc/qemu/target/riscv/tcg/
H A Dtcg-cpu.c310 edata->name, env->mhartid); in riscv_cpu_disable_priv_spec_isa_exts()
804 enabled = test_bit(cpu->env.mhartid, rule->enabled); in cpu_enable_implied_rule()
847 bitmap_set(rule->enabled, cpu->env.mhartid, 1); in cpu_enable_implied_rule()