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Searched refs:memmap (Results 1 – 25 of 37) sorted by relevance

12

/openbmc/qemu/hw/riscv/
H A Dopentitan.c83 const MemMapEntry *memmap = ibex_memmap; in opentitan_machine_init() local
100 memmap[IBEX_DEV_RAM].base, machine->ram); in opentitan_machine_init()
103 hwaddr firmware_load_addr = memmap[IBEX_DEV_RAM].base; in opentitan_machine_init()
110 memmap[IBEX_DEV_RAM].base, in opentitan_machine_init()
147 const MemMapEntry *memmap = ibex_memmap; in lowrisc_ibex_soc_realize() local
165 memmap[IBEX_DEV_ROM].size, &error_fatal); in lowrisc_ibex_soc_realize()
167 memmap[IBEX_DEV_ROM].base, &s->rom); in lowrisc_ibex_soc_realize()
171 memmap[IBEX_DEV_FLASH].size, &error_fatal); in lowrisc_ibex_soc_realize()
174 memmap[IBEX_DEV_FLASH_VIRTUAL].size); in lowrisc_ibex_soc_realize()
175 memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base, in lowrisc_ibex_soc_realize()
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H A Dmicrochip_pfsoc.c196 const MemMapEntry *memmap = microchip_pfsoc_memmap; in microchip_pfsoc_soc_realize() local
219 memmap[MICROCHIP_PFSOC_RSVD0].size, &error_fatal); in microchip_pfsoc_soc_realize()
221 memmap[MICROCHIP_PFSOC_RSVD0].base, in microchip_pfsoc_soc_realize()
226 memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_fatal); in microchip_pfsoc_soc_realize()
228 memmap[MICROCHIP_PFSOC_E51_DTIM].base, in microchip_pfsoc_soc_realize()
233 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, in microchip_pfsoc_soc_realize()
234 memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); in microchip_pfsoc_soc_realize()
236 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, in microchip_pfsoc_soc_realize()
237 memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); in microchip_pfsoc_soc_realize()
239 memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, in microchip_pfsoc_soc_realize()
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H A Dsifive_e.c76 const MemMapEntry *memmap = sifive_e_memmap; in sifive_e_machine_init() local
96 memmap[SIFIVE_E_DEV_DTIM].base, machine->ram); in sifive_e_machine_init()
115 memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); in sifive_e_machine_init()
120 memmap[SIFIVE_E_DEV_DTIM].base, in sifive_e_machine_init()
197 const MemMapEntry *memmap = sifive_e_memmap; in sifive_e_soc_realize() local
207 memmap[SIFIVE_E_DEV_MROM].size, &error_fatal); in sifive_e_soc_realize()
209 memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom); in sifive_e_soc_realize()
212 s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base, in sifive_e_soc_realize()
222 memmap[SIFIVE_E_DEV_PLIC].size); in sifive_e_soc_realize()
223 riscv_aclint_swi_create(memmap[SIFIVE_E_DEV_CLINT].base, in sifive_e_soc_realize()
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H A Dsifive_u.c95 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, in create_fdt() argument
155 (long)memmap[SIFIVE_U_DEV_DRAM].base); in create_fdt()
158 memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base, in create_fdt()
210 (long)memmap[SIFIVE_U_DEV_CLINT].base); in create_fdt()
215 0x0, memmap[SIFIVE_U_DEV_CLINT].base, in create_fdt()
216 0x0, memmap[SIFIVE_U_DEV_CLINT].size); in create_fdt()
223 (long)memmap[SIFIVE_U_DEV_OTP].base); in create_fdt()
227 0x0, memmap[SIFIVE_U_DEV_OTP].base, in create_fdt()
228 0x0, memmap[SIFIVE_U_DEV_OTP].size); in create_fdt()
235 (long)memmap[SIFIVE_U_DEV_PRCI].base); in create_fdt()
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H A Dxiangshan_kmh.c60 const MemMapEntry *memmap = xiangshan_kmh_memmap; in xiangshan_kmh_create_aia() local
65 addr = memmap[XIANGSHAN_KMH_IMSIC_M].base; in xiangshan_kmh_create_aia()
72 addr = memmap[XIANGSHAN_KMH_IMSIC_S].base; in xiangshan_kmh_create_aia()
81 aplic_m = riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_M].base, in xiangshan_kmh_create_aia()
82 memmap[XIANGSHAN_KMH_APLIC_M].size, in xiangshan_kmh_create_aia()
87 riscv_aplic_create(memmap[XIANGSHAN_KMH_APLIC_S].base, in xiangshan_kmh_create_aia()
88 memmap[XIANGSHAN_KMH_APLIC_S].size, in xiangshan_kmh_create_aia()
99 const MemMapEntry *memmap = xiangshan_kmh_memmap; in xiangshan_kmh_soc_realize() local
113 serial_mm_init(system_memory, memmap[XIANGSHAN_KMH_UART0].base, 2, in xiangshan_kmh_soc_realize()
118 riscv_aclint_swi_create(memmap[XIANGSHAN_KMH_CLINT].base, in xiangshan_kmh_soc_realize()
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H A Dspike.c51 static void create_fdt(SpikeState *s, const MemMapEntry *memmap, in create_fdt() argument
83 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); in create_fdt()
148 addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); in create_fdt()
158 clint_addr = memmap[SPIKE_CLINT].base + in create_fdt()
159 (memmap[SPIKE_CLINT].size * socket); in create_fdt()
165 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); in create_fdt()
196 const MemMapEntry *memmap = spike_memmap; in spike_board_init() local
200 target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base; in spike_board_init()
201 hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base; in spike_board_init()
251 memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, in spike_board_init()
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H A Dvirt.c169 hwaddr flashsize = s->memmap[VIRT_FLASH].size / 2; in virt_flash_map()
170 hwaddr flashbase = s->memmap[VIRT_FLASH].base; in virt_flash_map()
310 addr = s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); in create_fdt_socket_memory()
341 clint_addr = s->memmap[VIRT_CLINT].base + in create_fdt_socket_clint()
342 s->memmap[VIRT_CLINT].size * socket; in create_fdt_socket_clint()
349 2, clint_addr, 2, s->memmap[VIRT_CLINT].size); in create_fdt_socket_clint()
383 addr = s->memmap[VIRT_CLINT].base + in create_fdt_socket_aclint()
384 (s->memmap[VIRT_CLINT].size * socket); in create_fdt_socket_aclint()
401 addr = s->memmap[VIRT_CLINT].base + in create_fdt_socket_aclint()
405 addr = s->memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + in create_fdt_socket_aclint()
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H A Dvirt-acpi-build.c79 imsic_socket_addr = s->memmap[VIRT_IMSIC_S].base + in riscv_acpi_madt_add_rintc()
242 .base_addr.addr = s->memmap[VIRT_UART0].base, in spcr_setup()
448 const MemMapEntry *memmap = s->memmap; in build_dsdt() local
465 fw_cfg_acpi_dsdt_add(scope, &memmap[VIRT_FW_CFG]); in build_dsdt()
470 acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_PLIC].base, in build_dsdt()
471 memmap[VIRT_PLIC].size, "RSCV0001"); in build_dsdt()
473 acpi_dsdt_add_plic_aplic(scope, socket_count, memmap[VIRT_APLIC_S].base, in build_dsdt()
474 memmap[VIRT_APLIC_S].size, "RSCV0002"); in build_dsdt()
477 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART0], UART0_IRQ); in build_dsdt()
479 acpi_dsdt_add_iommu_sys(scope, &memmap[VIRT_IOMMU_SYS], IOMMU_SYS_IRQ); in build_dsdt()
[all …]
/openbmc/qemu/hw/tricore/
H A Dtc27x_soc.c106 sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size); in tc27x_soc_init_memory_mapping()
108 sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size); in tc27x_soc_init_memory_mapping()
110 sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size); in tc27x_soc_init_memory_mapping()
112 sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size); in tc27x_soc_init_memory_mapping()
114 sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size); in tc27x_soc_init_memory_mapping()
116 sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size); in tc27x_soc_init_memory_mapping()
120 sc->memmap[TC27XD_DCACHE2].base, sc->memmap[TC27XD_DCACHE2].size); in tc27x_soc_init_memory_mapping()
122 sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size); in tc27x_soc_init_memory_mapping()
124 sc->memmap[TC27XD_PCACHE2].base, sc->memmap[TC27XD_PCACHE2].size); in tc27x_soc_init_memory_mapping()
126 sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size); in tc27x_soc_init_memory_mapping()
[all …]
/openbmc/qemu/hw/arm/
H A Dallwinner-h3.c190 rom_size, s->memmap[AW_H3_DEV_SRAM_A1], in allwinner_h3_bootrom_setup()
198 s->memmap = allwinner_h3_memmap; in allwinner_h3_init()
275 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]); in allwinner_h3_realize()
276 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]); in allwinner_h3_realize()
277 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]); in allwinner_h3_realize()
278 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]); in allwinner_h3_realize()
325 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]); in allwinner_h3_realize()
338 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1], in allwinner_h3_realize()
340 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2], in allwinner_h3_realize()
342 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C], in allwinner_h3_realize()
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H A Daspeed_ast2600.c318 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], in aspeed_soc_ast2600_realize()
323 sc->memmap[ASPEED_DEV_IOMEM], in aspeed_soc_ast2600_realize()
328 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); in aspeed_soc_ast2600_realize()
333 sc->memmap[ASPEED_DEV_EMMC_BC], 0x1000); in aspeed_soc_ast2600_realize()
389 sc->memmap[ASPEED_DEV_SRAM], &s->sram); in aspeed_soc_ast2600_realize()
393 sc->memmap[ASPEED_DEV_DPMCU], in aspeed_soc_ast2600_realize()
400 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); in aspeed_soc_ast2600_realize()
406 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); in aspeed_soc_ast2600_realize()
417 sc->memmap[ASPEED_DEV_TIMER1]); in aspeed_soc_ast2600_realize()
427 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); in aspeed_soc_ast2600_realize()
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H A Daspeed_ast10x0.c205 sc->memmap[ASPEED_DEV_IOMEM], in aspeed_soc_ast1030_realize()
208 "aspeed.sbc", sc->memmap[ASPEED_DEV_SBC], in aspeed_soc_ast1030_realize()
229 sc->memmap[ASPEED_DEV_SRAM], in aspeed_soc_ast1030_realize()
237 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM], in aspeed_soc_ast1030_realize()
244 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); in aspeed_soc_ast1030_realize()
253 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); in aspeed_soc_ast1030_realize()
265 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i3c), 0, sc->memmap[ASPEED_DEV_I3C]); in aspeed_soc_ast1030_realize()
278 sc->memmap[ASPEED_DEV_PECI]); in aspeed_soc_ast1030_realize()
286 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]); in aspeed_soc_ast1030_realize()
323 sc->memmap[ASPEED_DEV_TIMER1]); in aspeed_soc_ast1030_realize()
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H A Daspeed_ast2400.c267 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], in aspeed_ast2400_soc_realize()
272 sc->memmap[ASPEED_DEV_IOMEM], in aspeed_ast2400_soc_realize()
277 sc->memmap[ASPEED_DEV_VIDEO], 0x1000); in aspeed_ast2400_soc_realize()
295 sc->memmap[ASPEED_DEV_SRAM], &s->sram); in aspeed_ast2400_soc_realize()
301 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]); in aspeed_ast2400_soc_realize()
307 aspeed_mmio_map(s, SYS_BUS_DEVICE(&a->vic), 0, sc->memmap[ASPEED_DEV_VIC]); in aspeed_ast2400_soc_realize()
317 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]); in aspeed_ast2400_soc_realize()
328 sc->memmap[ASPEED_DEV_TIMER1]); in aspeed_ast2400_soc_realize()
338 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]); in aspeed_ast2400_soc_realize()
353 aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]); in aspeed_ast2400_soc_realize()
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H A Dallwinner-r40.c256 rom_size, s->memmap[AW_R40_DEV_SRAM_A1], in allwinner_r40_bootrom_setup()
268 s->memmap = allwinner_r40_memmap; in allwinner_r40_init()
348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_R40_DEV_GIC_DIST]); in allwinner_r40_realize()
349 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_R40_DEV_GIC_CPU]); in allwinner_r40_realize()
350 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_R40_DEV_GIC_HYP]); in allwinner_r40_realize()
351 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_R40_DEV_GIC_VCPU]); in allwinner_r40_realize()
398 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_R40_DEV_PIT]); in allwinner_r40_realize()
408 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sramc), 0, s->memmap[AW_R40_DEV_SRAMC]); in allwinner_r40_realize()
419 s->memmap[AW_R40_DEV_SRAM_A1], &s->sram_a1); in allwinner_r40_realize()
421 s->memmap[AW_R40_DEV_SRAM_A2], &s->sram_a2); in allwinner_r40_realize()
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H A Dvirt-acpi-build.c142 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, in acpi_dsdt_add_pci() argument
157 .mmio32 = memmap[VIRT_PCIE_MMIO], in acpi_dsdt_add_pci()
158 .pio = memmap[VIRT_PCIE_PIO], in acpi_dsdt_add_pci()
159 .ecam = memmap[ecam_id], in acpi_dsdt_add_pci()
166 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO]; in acpi_dsdt_add_pci()
214 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base; in acpi_dsdt_add_tpm()
438 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8); in build_iort()
545 .base_addr.addr = vms->memmap[VIRT_UART0].base, in spcr_setup()
604 mem_base = vms->memmap[VIRT_MEM].base; in build_srat()
737 vms->memmap[VIRT_UART0].base); in build_dbg2()
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H A Daspeed_ast27x0.c417 sc->memmap[ASPEED_DEV_SDRAM] + ram_size, in aspeed_soc_ast2700_dram_init()
422 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); in aspeed_soc_ast2700_dram_init()
603 sc->memmap[ASPEED_GIC_DIST]); in aspeed_soc_ast2700_gic_realize()
605 sc->memmap[ASPEED_GIC_REDIST]); in aspeed_soc_ast2700_gic_realize()
729 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SPI_BOOT], in aspeed_soc_ast2700_realize()
758 sc->memmap[ASPEED_DEV_INTC]); in aspeed_soc_ast2700_realize()
766 sc->memmap[ASPEED_DEV_INTCIO]); in aspeed_soc_ast2700_realize()
807 sc->memmap[ASPEED_DEV_SDMC]); in aspeed_soc_ast2700_realize()
821 sc->memmap[ASPEED_DEV_SRAM], &s->sram); in aspeed_soc_ast2700_realize()
829 sc->memmap[ASPEED_DEV_VBOOTROM], &s->vbootrom); in aspeed_soc_ast2700_realize()
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H A Daspeed_ast27x0-tsp.c200 sc->memmap[ASPEED_DEV_SDRAM], in aspeed_soc_ast27x0tsp_realize()
204 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], in aspeed_soc_ast27x0tsp_realize()
208 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], in aspeed_soc_ast27x0tsp_realize()
217 sc->memmap[ASPEED_DEV_INTC]); in aspeed_soc_ast27x0tsp_realize()
225 sc->memmap[ASPEED_DEV_INTCIO]); in aspeed_soc_ast27x0tsp_realize()
255 sc->memmap[ASPEED_DEV_TIMER1], 0x200); in aspeed_soc_ast27x0tsp_realize()
258 sc->memmap[ASPEED_DEV_IPC0], 0x1000); in aspeed_soc_ast27x0tsp_realize()
261 sc->memmap[ASPEED_DEV_IPC1], 0x1000); in aspeed_soc_ast27x0tsp_realize()
264 sc->memmap[ASPEED_DEV_SCUIO], 0x1000); in aspeed_soc_ast27x0tsp_realize()
288 sc->memmap = aspeed_soc_ast27x0tsp_memmap; in aspeed_soc_ast27x0tsp_class_init()
H A Daspeed_ast27x0-ssp.c203 sc->memmap[ASPEED_DEV_SDRAM], in aspeed_soc_ast27x0ssp_realize()
207 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SRAM], in aspeed_soc_ast27x0ssp_realize()
211 memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SCU], in aspeed_soc_ast27x0ssp_realize()
220 sc->memmap[ASPEED_DEV_INTC]); in aspeed_soc_ast27x0ssp_realize()
228 sc->memmap[ASPEED_DEV_INTCIO]); in aspeed_soc_ast27x0ssp_realize()
258 sc->memmap[ASPEED_DEV_TIMER1], 0x200); in aspeed_soc_ast27x0ssp_realize()
261 sc->memmap[ASPEED_DEV_IPC0], 0x1000); in aspeed_soc_ast27x0ssp_realize()
264 sc->memmap[ASPEED_DEV_IPC1], 0x1000); in aspeed_soc_ast27x0ssp_realize()
267 sc->memmap[ASPEED_DEV_SCUIO], 0x1000); in aspeed_soc_ast27x0ssp_realize()
291 sc->memmap = aspeed_soc_ast27x0ssp_memmap; in aspeed_soc_ast27x0ssp_class_init()
H A Dvirt.c549 vms->memmap[VIRT_GIC_ITS].base); in fdt_add_its_gic_node()
556 2, vms->memmap[VIRT_GIC_ITS].base, in fdt_add_its_gic_node()
557 2, vms->memmap[VIRT_GIC_ITS].size); in fdt_add_its_gic_node()
568 vms->memmap[VIRT_GIC_V2M].base); in fdt_add_v2m_gic_node()
575 2, vms->memmap[VIRT_GIC_V2M].base, in fdt_add_v2m_gic_node()
576 2, vms->memmap[VIRT_GIC_V2M].size); in fdt_add_v2m_gic_node()
590 vms->memmap[VIRT_GIC_DIST].base); in fdt_add_gic_node()
608 2, vms->memmap[VIRT_GIC_DIST].base, in fdt_add_gic_node()
609 2, vms->memmap[VIRT_GIC_DIST].size, in fdt_add_gic_node()
610 2, vms->memmap[VIRT_GIC_REDIST].base, in fdt_add_gic_node()
[all …]
H A Dorangepi.c73 object_property_set_uint(OBJECT(h3), "ram-addr", h3->memmap[AW_H3_DEV_SDRAM], in orangepi_init()
92 memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_DEV_SDRAM], in orangepi_init()
100 orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM]; in orangepi_init()
H A Dbananapi_m2u.c86 r40->memmap[AW_R40_DEV_SDRAM], &error_abort); in bpim2u_init()
120 r40->memmap[AW_R40_DEV_SDRAM], machine->ram); in bpim2u_init()
122 bpim2u_binfo.loader_start = r40->memmap[AW_R40_DEV_SDRAM]; in bpim2u_init()
H A Daspeed_soc_common.c45 qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2); in aspeed_soc_uart_realize()
52 aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]); in aspeed_soc_uart_realize()
106 sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container); in aspeed_soc_dram_init()
/openbmc/qemu/hw/vmapple/
H A Dvmapple.c60 const MemMapEntry *memmap; member
99 static const MemMapEntry memmap[] = { variable
159 sysbus_mmio_map(bdif_sb, 0, vms->memmap[VMAPPLE_BDOOR].base); in create_bdif()
173 sysbus_mmio_map(pvpanic, 0, vms->memmap[VMAPPLE_PVPANIC].base); in create_pvpanic()
188 sysbus_mmio_map(cfg, 0, vms->memmap[VMAPPLE_CONFIG].base); in create_cfg()
212 sysbus_mmio_map(gfx, 0, vms->memmap[VMAPPLE_APV_GFX].base); in create_gfx()
213 sysbus_mmio_map(gfx, 1, vms->memmap[VMAPPLE_APV_IOSFC].base); in create_gfx()
225 sysbus_mmio_map(aes, 0, vms->memmap[VMAPPLE_AES_1].base); in create_aes()
226 sysbus_mmio_map(aes, 1, vms->memmap[VMAPPLE_AES_2].base); in create_aes()
255 vms->memmap[VMAPPLE_GIC_REDIST].size / GICV3_REDIST_SIZE; in create_gic()
[all …]
/openbmc/qemu/hw/mips/
H A Dboston.c513 const MemMapEntry *memmap, int *dt_size) in create_fdt() argument
562 memmap[BOSTON_PCIE0].base, memmap[BOSTON_PCIE0].size, in create_fdt()
563 memmap[BOSTON_PCIE0_MMIO].base, memmap[BOSTON_PCIE0_MMIO].size); in create_fdt()
566 memmap[BOSTON_PCIE1].base, memmap[BOSTON_PCIE1].size, in create_fdt()
567 memmap[BOSTON_PCIE1_MMIO].base, memmap[BOSTON_PCIE1_MMIO].size); in create_fdt()
570 memmap[BOSTON_PCIE2].base, memmap[BOSTON_PCIE2].size, in create_fdt()
571 memmap[BOSTON_PCIE2_MMIO].base, memmap[BOSTON_PCIE2_MMIO].size); in create_fdt()
575 memmap[BOSTON_GIC].base); in create_fdt()
578 qemu_fdt_setprop_cells(fdt, gic_name, "reg", memmap[BOSTON_GIC].base, in create_fdt()
579 memmap[BOSTON_GIC].size); in create_fdt()
[all …]
/openbmc/qemu/hw/dma/
H A Dsoc_dma.c80 } *memmap; member
114 lo = dma->memmap; in soc_dma_lookup()
133 while (entry < dma->memmap + dma->memmap_size && in soc_dma_ch_update_type()
265 dma->memmap = g_realloc(dma->memmap, sizeof(*entry) * in soc_dma_port_add_fifo()
284 while (entry < dma->memmap + dma->memmap_size && in soc_dma_port_add_fifo()
297 (uint8_t *) (dma->memmap + dma->memmap_size ++) - in soc_dma_port_add_fifo()
315 dma->memmap = g_realloc(dma->memmap, sizeof(*entry) * in soc_dma_port_add_mem()
344 while (entry < dma->memmap + dma->memmap_size && in soc_dma_port_add_mem()
350 (uint8_t *) (dma->memmap + dma->memmap_size ++) - in soc_dma_port_add_mem()

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