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Searched refs:membaseconfig0 (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock_init.h123 unsigned membaseconfig0; member
H A Ddmc_init_ddr3.c112 writel(mem->membaseconfig0, &dmc->membaseconfig0); in ddr3_mem_ctrl_init()
578 writel(val, &tzasc0->membaseconfig0); in ddr3_mem_ctrl_init()
579 writel(val, &tzasc1->membaseconfig0); in ddr3_mem_ctrl_init()
H A Dclock_init_exynos5.c350 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
453 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Ddmc.h174 unsigned int membaseconfig0; member
424 unsigned int membaseconfig0; member